Quantum Dot Gate Field-effect Transistor Research Articles

Fabrication and Characterization of nMOS Inverters Utilizing Quantum Dot Gate Field Effect Transistor (QDGFET) for SRAM Device

This paper presents experimental results of nMOS quantum dot gate field effect transistor (QDGFET) based inverter devices for SRAM devices. A three-state inverter device was fabricated and tested with Si/SiO2 quantum dots. The work performed here builds off previous works performed with Si/SiO2 dot-based inverters which used two layers of quantum dots. This research explores multi-state SRAM device operation. A three-state (Si QDs) and a four-state (Si and Ge QDs) inverter are described, and they will allow for multistate logic devices to be utilized in everyday logic chips, which will require less devices to perform the same tasks as conventional devices, double the capacity of the device, and require less power, which will generate less of a thermal footprint. The data of the Half Cell SRAM, comprised of one access transistor and an inverter along with a capacitor, is presented here.

Modeling of Multi-State Si and Ge Cladded Quantum Dot Gate FETs Using Verilog and ABM Simulations

Quantum dot gate (QDG) field-effect transistors (FETs) fabricated using Si and Ge quantum dot layers, self-assembled in the gate region over the tunnel oxide, have exhibited 3- and 4-state behavior applicable for ternary and quaternary logic, respectively. This paper presents simulation of QDG-FETs comprising mixed Ge and Si quantum dot layers over tunnel oxide using an analog behavior model (ABM) and Verilog model. The simulations reproduce the experimental I-V characteristics of a fabricated mixed dot QDG-FET. GeOx-cladded Ge quantum dot layer is in interface to the tunnel oxide and is deposited over with a SiOx-cladded Si quantum dot layer. The fabricated QDG-FET has one source and one gate. The ABM simulation models QDG-FET using conventional BSIM 3V3 FETs with capacitances and other device parameters. In addition, VERILOG model is presented. The agreement in circuit and quantum simulations and experimental data will further advance in the designing of QDG-FET-based analog-to-digital converters (ADCs), 2-bit logic gates and SRAM cells.

Quantum Dot Gate FET Based Multi-Value Logic Sequential Circuits

The design of multi value logic sequential circuits based on QG-FET (Quantum dot Gate Field Effect Transistor) is discussed here. The QG-FET produces an intermediate state in between the two stable states(i.e.) ON & OFF, this is happening due to change in the threshold voltage over this range. The design of various sequential circuits using QDGFET which includes ternary D-flipflop and ternary right shift register is discussed. The proposed design of sequential circuits using QDGFET results an improved circuit parameter and less circuit elements in the implantation. The three state QG-FET will increase the bit handling capability of the device due to increase in number of states. So that, with less circuit elements at a time we can handle more number of bits.

Dual Quantum Dot Superlattice

In this paper, we propose a structure using four layers of quantum dots on crystalline silicon. The quantum dots site-specifically self-assembled in the p-type material due to the electrostatic attraction. This quantum dot super lattice (QDSL) structure will be constructed using a mixed layer of Germanium (Ge) and Silicon (Si) dots. Atomic Force Microscopy results will show the accurate stack height formed from individual and multi stacked layers. This is the first novel characterization of 4 layers of 2 separate self assemblies. This was also applied to a quantum dot gate field effect transistor (QDG-FET).

Ternary static random access memory using quantum dot gate field‐effect transistor

Quantum dot gate field-effect transistor (QDGFET) generates three states in their transfer characteristics. A successful model can explain the generation of third state in the transfer characteristics of the QDGFET. The innovative circuit design using QDGFET can be used to design different ternary logic. This Letter discusses the design of ternary logic static random access memory using QDGFET.

Three‐state quantum dot gate field‐effect transistor in silicon‐on‐insulator

This paper presents the observation of intermediate state in the quantum dot gate field-effect transistors (QDGFETs) in silicon-on-insulator (SOI) substrate. Silicon dioxide (SiO2)-cladded silicon (Si) quantum dots (QDs) are site-specifically self-assembled on the top of SiO2 tunnel gate insulator on SOI substrates. Charge carrier tunnelling from the inversion channel to the QD layers on top of the gate insulator is responsible for the generation of intermediate state. Charge tunnelling is also verified by the C–V characteristics of the MOS device having same insulator structure as the gate region of the QDGFET. Considering the transfer of charge carriers from the inversion channel to two layers of SiO2-cladded Si QDs, a model based on self-consistent solution of Schrodinger and Poisson equations, is also presented, to explain the generation of intermediate state.

Novel Multistate Quantum Dot Gate FETs Using SiO2 and Lattice-Matched ZnS-ZnMgS-ZnS as Gate Insulators

Multistate behavior has been achieved in quantum dot gate field-effect transistor (QDGFET) configurations using either SiOx-cladded Si or GeOx-cladded Ge quantum dots (QDs) with asymmetric dot sizes. An alternative method is to use both SiOx-cladded Si and GeOx-cladded Ge QDs in QDGFETs. In this paper, we present experimental verification of four-state behavior observed in a QDGFET with cladded Si and Ge dots site-specifically self-assembled in the gate region over a thin SiO2 tunnel layer on a Si substrate. This paper also investigates the use of lattice-matched high-κ ZnS-ZnMgS-ZnS layers as a gate insulator in mixed-dot Si QDGFETs. Quantum-mechanical simulation of the transfer characteristic (ID–VG) shows four-state behavior with two intermediate states between the conventional ON and OFF states.

Fabrication and Simulation of an Indium Gallium Arsenide Quantum-Dot-Gate Field-Effect Transistor (QDG-FET) with ZnMgS as a Tunnel Gate Insulator

An indium gallium arsenide quantum-dot-gate field-effect transistor using Zn0.95Mg0.05S as the gate insulator is presented in this paper, showing three output states which can be used in multibit logic applications. The spatial wavefunction switching effect in this transistor has been investigated, and modeling simulations have shown supporting evidence that additional output states can be achieved in one transistor.

Design of Ternary Logic Combinational Circuits Based on Quantum Dot Gate FETs

In this paper, we discuss logic circuit designs using the circuit model of three-state quantum dot gate field effect transistors (QDGFETs). QDGFETs produce one intermediate state between the two normal stable ON and OFF states due to a change in the threshold voltage over this range. We have developed a simplified circuit model that accounts for this intermediate state. Interesting logic can be implemented using QDGFETs. In this paper, we discuss the designs of various two-input three-state QDGFET gates, including NAND- and NOR-like operations and their application in different combinational circuits like decoder, multiplier, adder, and so on. Increased number of states in three-state QDGFETs will increase the number of bit-handling capability of this device and will help us to handle more number of bits at a time with less circuit elements.

Improved device structure of quantum dot gate FET to obtain more stable intermediate state

Quantum dot gate field effect transistors (QDGFETs) produce three states in their transfer characteristics, which make them suitable for ternary logic circuit implementation. The basic problem of a QDGFET is the dissociation of quantum dots in the gate region. An improved device structure of a QDGFET is introduced which can solve this problem. The three-state behaviour of the QDGFET can be observed even after ten months. The experimental results are compared and show the improved nature of the device.

ZnS-ZnMgS-ZnS Lattice-Matched Gate Insulator as an Alternative for Silicon Dioxide on Silicon in Quantum Dot Gate FETs (QDGFETs)

This paper presents characteristics of two fabricated Si quantum dot gate field-effect transistors, one with SiOx-cladded Si dots on silicon dioxide as the gate insulator, and another with the same quantum dots on lattice-matched high-κ ZnS-ZnMgS-ZnS as the gate insulator. Simulations show that the oxide thickness should be within 80 A to generate a third state in the transfer characteristic of the quantum dot gate field-effect transistor. In the practical device, the silicon dioxide thickness varies between 20 A and 40 A. In this work we use high-κ dielectric thickness around 75 A to 80 A, which is equivalent to 32 A to 35 A of silicon dioxide.

Indium Gallium Arsenide Quantum Dot Gate Field-Effect Transistor Using II–VI Tunnel Insulators Showing Three-State Behavior

This paper presents an indium gallium arsenide (InGaAs) quantum dot gate field-effect transistor (QDG-FET) that exhibits an intermediate “i” state in addition to the conventional ON and OFF states. The QDG-FET utilized a II–VI gate insulator stack consisting of lattice-matched ZnSe/ZnS/ZnMgS/ZnS/ZnSe for its high-κ and wide-bandgap properties. Germanium oxide (GeOx)-cladded germanium quantum dots were self-assembled over the gate insulator stack, and they allow for the three-state behavior of the device. Electrical characteristics of the fabricated device are also presented.

Fabrication and Circuit Modeling of NMOS Inverter Based on Quantum Dot Gate Field-Effect Transistors

This paper presents the fabrication of a negative-channel metal–oxide–semiconductor (NMOS) inverter based on quantum dot gate field-effect transistors (QDG-FETs). A QDG-FET produces one intermediate state in its transfer characteristic. NMOS inverters based on a QDG-FET produce three states in their transfer characteristic. The generation of the third state in the inverter characteristic makes this a promising circuit element for multivalued logic implementation. A circuit simulation result based on the Berkley simulation (BSIM) circuit model of the QDG-FET is also presented in this paper, predicting the fabricated device characteristic.

Future Semiconductor Devices for Multi-Valued Logic Circuit Design

This paper introduces future devices for multi-valued logic implementation. Quantum dot gate field effect transistor (QDGFET) works based on the change in threshold voltage due to stored charge in the quantum dots in the gate region. Quantum dot channel field effect transistor (QDCFET) produces more number of states in their transfer characteristics because of charge flow through the mini-band structure formed by the overlapping energy bands of the neighboring quantum dots in the channel region of the FET. On the other hand spatial wave-function switched field effect transistor (SWSFET) produces more number of states in its transfer characteristic based on the switching of charge carriers from one channel to other channel of the device. In this paper we discuss QDGFET, QDCFET and SWSFET in detail to explore their application in future multi-valued logic circuits.

APPLICATION OF 25 NM QUANTUM DOT GATE FETs TO THE DESIGN OF ADC AND DAC CIRCUITS

This paper describes design of analog-to-digital converters (ADCs) and digital-to-analog onverters (DACs) using field-effect transistors that exhibit three states in their transfer characteristics. An intermediate state " i " has been observed in the transfer characteristics (drain current-gate voltage) of FETs when two layers of cladded quantum dots (e.g. SiO x - Si and GeO x - Ge ) are introduced in the gate region above the tunnel insulator between the source and drain regions. Three states in such a transistor, defined as quantum dot gate field-effect transistor (QDG-FET) include two stable states (ON and OFF) and a low-current saturation state " i " in its transfer characteristics. QDG-FETs are quite different in construction than nanodot based nonvolatile memories, reported in the literature, where the quantum dots are sandwiched between a tunnel gate insulator and a relatively thick control gate dielectric. In this paper we present analog-to-digital converters (ADCs) using comparators based on QDG-FETs. A comparator is designed with fewer three-state QDG-FETs. Designs of 3-bit ADC, using 25 nm QDG-FETs, are simulated showing a signal-to-noise ratio (SNR) of ~18. In addition, the R-2R ladder problem, encountered in conventional analog-to digital converters (ADCs), is absent in QDG-FET based architecture.

Three-State Quantum Dot Gate FETs Using ZnS-ZnMgS Lattice-Matched Gate Insulator on Silicon

This paper presents the three-state behavior of quantum dot gate field-effect transistors (FETs). GeOx-cladded Ge quantum dots (QDs) are site-specifically self-assembled over lattice-matched ZnS-ZnMgS high-κ gate insulator layers grown by metalorganic chemical vapor deposition (MOCVD) on silicon substrates. A model of three-state behavior manifested in the transfer characteristics due to the quantum dot gate is also presented. The model is based on the transfer of carriers from the inversion channel to two layers of cladded GeOx-Ge quantum dots.

Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II–VI Gate Insulators

This paper presents the successful use of ZnS/ZnMgS and other II-VI layers (lattice-matched or pseudomorphic) as high-k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.