APPLICATION OF 25 NM QUANTUM DOT GATE FETs TO THE DESIGN OF ADC AND DAC CIRCUITS

Abstract

This paper describes design of analog-to-digital converters (ADCs) and digital-to-analog onverters (DACs) using field-effect transistors that exhibit three states in their transfer characteristics. An intermediate state " i " has been observed in the transfer characteristics (drain current-gate voltage) of FETs when two layers of cladded quantum dots (e.g. SiO x - Si and GeO x - Ge ) are introduced in the gate region above the tunnel insulator between the source and drain regions. Three states in such a transistor, defined as quantum dot gate field-effect transistor (QDG-FET) include two stable states (ON and OFF) and a low-current saturation state " i " in its transfer characteristics. QDG-FETs are quite different in construction than nanodot based nonvolatile memories, reported in the literature, where the quantum dots are sandwiched between a tunnel gate insulator and a relatively thick control gate dielectric. In this paper we present analog-to-digital converters (ADCs) using comparators based on QDG-FETs. A comparator is designed with fewer three-state QDG-FETs. Designs of 3-bit ADC, using 25 nm QDG-FETs, are simulated showing a signal-to-noise ratio (SNR) of ~18. In addition, the R-2R ladder problem, encountered in conventional analog-to digital converters (ADCs), is absent in QDG-FET based architecture.