Quantum-dot Cellular Automata Research Articles

Efficient design of a reversible 2-to-4 decoder in quantum-dot cellular automata using Toffoli gates

This research presents an optimized design of a 2-to-4 decoder in Quantum-dot Cellular Automata (QCA) using a new formula developed from the Reversible. The proposed QCA decoder architecture employs 112 cells and occupies an area of 0.13μm², achieving a significant reduction in size compared to previous designs. The circuit is designed using a single-layer approach, enhancing its efficiency and minimizing power dissipation. Simulation results using the QCA Designer simulator version 2.0.3 demonstrate the enhanced functionality of the suggested decoder in regard to functionality and also efficiency, making it a promising candidate for future nanoscale integrated circuit applications.

Implementation of adders using XOR gates in quantum-dot cellular automata with physical verification

Abstract This paper presents a promising approach to nanoscale computing, offering significant advantages through the QCA technology. It suggests a highly efficient, scalable, and reliable multilayered QCA half and full adder circuits, leveraging a three-input QCA XOR gate. The proposed full adder layout demonstrates significant improvements in various parameters, including area, latency, and energy dissipation. In particular, it offers 17% greater area efficiency and utilizes 14 fewer cells compared to the best work existing work. We thoroughly evaluated energy dissipation using the QCADesigner-E tool. We also examined the cost functions, with a QCA-specific cost of 22 units, which is ~37% better than earlier designs. The architecture is strategically designed with externally accessible input and output nodes to ensure seamless scalability. Physical reliability is ensured through kink energy calculations for the suitability of higher-order circuit designs. Practical applications of the proposed blocks include their use in arithmetic logic units (ALUs), digital signal processors, and other modern processing and computing systems. This work sets a new benchmark for future developments in QCA technology, offering a robust, efficient, and versatile solution for advanced nano-processing and computing systems.

Pseudo random bit generator in QCA for high speed communications

Quantum-dot cellular automata (QCA) technology is another new technology in the field of nanoelectronics and quantum. With the help of this technology, basic to advanced digital circuits can be designed and implemented with low energy consumption and small area. Therefore, in this paper, a new design for a four- and eight-bit Linear feedback shift register (LFSR) or random counter, as well as a rising-edge-sensitive D flip-flop with the least possible number of cells and the smallest area, was presented. This paper first designs the proposed D flip-flop with 24 cells and an area of 0.01μm2, so that with the help of this flip-flop it can design four and eight-bit LFSR. This flip-flop is one of the most optimal and suitable designs in terms of area and number of cells. Then, in the second step, a four-bit LFSR with 144 cells and an area of 0.2μm2 was designed with the help of the proposed flip-flop in the most optimal possible state. Also, in the third step, an eight-bit LFSR with 281 cells and an area of 0.4μm2 has been implemented for the first time in QCA technology, which is among the best possible designs. All the designs and simulations of this article were done in QCADesigner version 2.0.3 software and with QCAPro software, the energy consumption of the proposed circuits.

New tile-based circuits converting BCD code to gray, excess-3, and aiken codes in quantum-dot cellular automata (QCA) nanotechnology

New tile-based circuits converting BCD code to gray, excess-3, and aiken codes in quantum-dot cellular automata (QCA) nanotechnology

Implementation of EXOR and Subsequent Modular Circuits for Application at Nanoscale Level

Evolving as an outperforming nanotechnology, quantum-dot cellular automata (QCA) is being efficiently used for the design and development of digital modules. This paper presents a novel design for an ultra-efficient exclusive-OR (EXOR) gate in QCA nanotechnology using the cell translation technique. The analysis for fault tolerance and power dissipation of the proposed design is also assessed. To establish the effectiveness of the proposed design, an extensive comparison with the existing designs is provided. As a test bench implementation, the proposed EXOR gate is available as a module for the development of a parity checker, a full subtractor, and a 4-input binary to gray (B2G) code converter in QCA. The cell count for the proposed design of the EXOR gate, full subtractor, parity checker, and 4-input B2G converter is 8, 35, 24, and 24, and the total area (µm2) is 0.0039, 0.0259, 0.01749, and 0.0129, respectively. The proposed EXOR gate design outclasses the hitherto prevailing designs both in terms of the operational parameters and the dissipation of energy. The design simulations have been performed in QCA Designer 2.0.3, and the energy dissipation analysis has been executed in QCA Designer-E and QCAPro.

Reliable Synchronous and Asynchronous Counter Design in QCA

Due to rapid growth in the integrated circuit (IC) industry, the demand for compact digital system design is high. However, the continued technology reductions made the feasibility of further scaling down transistor size more challenging. In response to the growing demand for ultra-compact IC designs, the revolutionary quantum-dot cellular automata (QCA) technology has emerged as a promising solution. In a digital era, the counters are widely adopted in the peer-to-peer process flow to establish a mechanism for generating unique values for each identifier/number. In this work, a unique synchronous and asynchronous counters architecture is proposed with a reliable D and T flip-flop design. The proposed QCA architecture is implemented and validated with the QCA designer tool. Furthermore, in QCA technology, unreliable QCA designs can lead to frequent errors and malfunctions in the implemented logic. To overcome this challenge, the proposed design prioritizes cell placement (the relative positions of QCA cells) to make the circuit more robust. As a result, the circuit can still produce the expected functionality even if some QCA cells malfunction. Hence, to ensure the reliability of the proposed QCA architecture, the missing cell defect analysis is carried out in comparison with existing state-of-the-art designs. Based on comparison results, the unique designs like the proposed multiplexer, D flip-flop and T flip-flop design exhibit success rates of 67.28, 77.04 and 85.15%, respectively. The experimental results demonstrate that the proposed counter-architecture outperforms existing architectures.

Efficient quantum-dot adder optimisation and analysis for future circuits

ABSTRACT In recent years, the rapid scaling of transistors has necessitated the exploration of advanced alternatives to Complementary metal oxide semiconductor(CMOS) technology for future progress. Quantum-dot cellular automata(QCA) technology has emerged as a promising solution, offering highly dense, high-speed, and low-power circuits. Among the critical digital building blocks, adder circuits play a crucial role in arithmetic and logic units. Consequently, optimising these circuits in terms of area, delay, and quantum cost is essential for the development of efficient designs. This paper presents effective multi-layer n-bit ripple carry adder(RCA) circuits, utilising full adder(FA) circuit. The outputs are generated in distinct layers and verified using the QCADesigner-Ev2.2 tool with bi-stable and coherence vector energy setups, employing Euler and Runge-Kutta methods.Additionally, the proposed designs are evaluated for various design metrics at three different scale factors(1,0.8889,and 0.7778), corresponding to cell sizes of 18 × 18 nm , 16 × 16 nm , and 14 × 14 nm respectively. The temperature’s impact on the average output polarisation of the FA is explored. The research demonstrates an n-bit-RCA surpassing existing designs with cost optimisations of 89.5%, 86%, and 90.3% for 4-bit,8-bit and 16-bit circuits, respectively. The paper also provides a thorough energy dissipation analysis for the proposed adder design.

Three different topologies for 4-bit counters in quantum-dot cellular automata technology

Abstract QCA (Quantum-dot Cellular Automata) technology is an innovative technology based on quantum principles and uses quantum dots as the basic units for information transfer. This technology enables the fabrication of electronic circuits at high speed, lower power consumption and smaller size. For this reason, in this article, for the first time, three types of counters are designed in QCA technology with the least cell and the smallest area. First, Johnson ring counter with 132 cells, area of 0.16 μ m 2 and a delay of 2 clock cycles, then synchronous counter with 192 cells and area of 0.2 μ m 2 and finally synchronous with reset capability with 267 cells and area of ​ 0.27 μ m 2 is designed. Also, the number of cells and the occupied area of the proposed designs have improved by 25.82 % and 35 % , respectively, compared to different authorities. As a result, the proposed designs are among the most optimal designs among different authorities. All the simulations were done in QCAPro and QCADesigner version 2.0.3 softwares.

Design of SRAM cell using an optimized D-latch in quantum-dot cellular automata (QCA) technology

A newer nanoscale technology called quantum-dot cellular automata (QCA) has been used by researchers to design digital circuits in place of the more traditional complementary metal–oxide semiconductor (CMOS) technology. This recent development in the technology change is due to the problems faced by CMOS technology in terms of power consumption and physical limitations. The advantages of QCA technology over CMOS technology are high density, low power consumption, high-speed operation, and less footprint area. This research provides a novel circuit for D-latch and static random access memory (SRAM) cells based on QCA technology. Initially, a D-latch circuit is proposed with a layout area of 0.01 μm2, a 0.5 clock cycle delay (latency), and a cell count of 18 QCA cells. Furthermore, an SRAM cell is proposed using the same D-latch circuit, which uses cell counts of 26 QCA cells and contributes to a layout area of 0.02 μm2 with a 0.75 clock cycle delay (latency). It is observed that our proposed circuits have a smaller layout area, fewer QCA cell counts, and a lower clock cycle delay (latency) than existing circuits.

Circuits for the spectroscopic readout of bits from molecular quantum-dot cellular automata

Molecular quantum-dot cellular automata (QCA) may provide high speed, low-power, classical information processing in the post-CMOS era. The readout of molecular QCA bits is challenging because the molecules may be much smaller than transistors and even single-electron transistors. This paper builds on a recent proposal for the spectroscopic readout of bits from asymmetric QCA molecules. Here, we propose circuits for fanning out a bit onto a large QCA circuit to increase the spectroscopic signal-to-noise ratio. As the number of molecules in a fanout circuit grows, the internal bias of each asymmetric cell accumulates, and the circuit may become stuck, tolerating only a very small internal bias. We also propose the use of an applied electric field to compensate for a candidate molecule’s internal bias, thereby restoring switchability, even when the internal bias is significant.

Multi-Layer QCA Reversible Full Adder-Subtractor Using Reversible Gates for Reliable Information Transfer and Minimal Power Dissipation on Universal Quantum Computer

The effects of quantum mechanics dominate nanoscale devices, where Moore’s law no longer holds true. Additionally, with the recent rapid development of quantum computers, the development of reversible gates to overcome the problems of energy and information loss and the nano-level quantum-dot cellular automata (QCA) technology to efficiently implement them are in the spotlight. In this study, a full adder-subtractor, a core operation of the arithmetic and logic unit (ALU), the most important hardware device in computer operations, is implemented as a circuit capable of reversible operation using QCA-based reversible gates. The proposed circuit consists of one reversible QCA gate and two Feynman gates and is designed as a multi-layer structure for efficient use of area and minimization of delay. The proposed circuit is tested on QCADesigner 2.0.3 and QCADesigner-E 2.2 and shows the best performance and lowest energy dissipation. In particular, it shows tremendous improvement rates of 180% and 562% in two representative standard design cost indicators compared to the best existing studies, and also shows the highest circuit average output polarization.

Optimal Computational Modeling and Simulation of QCA Reversible Gates for Information Reliability in Nano-Quantum Circuits

As the relationship between energy and information loss and reversible gates was revealed, much interest in reversible gate design arose, and as quantum-dot cellular automata (QCA) gained attention as a next-generation nano circuit design technology, various reversible gates based on QCA emerged. The proposed study optimizes the performance and design costs of existing QCA-based reversible gates including TR, RUG, PQR, and URG. According to most indicators, the proposed circuits showed significant improvement rates and outperformed existing studies. In particular, the proposed optimal TR, RUG, PQR, and URG showed performance improvements of 266%, 265%, 300%, and 144% in CostAD, respectively, compared with the best existing circuit. This shows outstanding improvement and superiority in terms of area and delay, which are the most important factors in the performance of nano-scale circuits that are becoming extremely miniaturized. Additionally, the exceptionally high-output polarization of the proposed circuits is an important indicator of the circuit’s expansion and connection and increases the circuit’s reliability.

An efficient nano-design of image processor circuits for morphology operations based on quantum dots

Quantum-dot cellular automata (QCA) are one of the most promising alternatives to traditional VLSI technology despite significant current obstacles. The QCA has the advantages of very low power dissipation, faster switching speed, and extremely low circuit area, which can be used in designing nano-scale image processing circuits. Morphological operations and processing of digital image processing is a significant topic for researchers because it is widely used for analyzing, enhancing, and modifying images to extract meaningful information or improve their visual quality. Image processing is also used for image retrieval and enhancement, image compression, object recognition, machine vision, and medical applications. QCA technology, as a new and leading technology with great potential, can play a fundamental role in morphological operations, processing digital images, image editing, medical imaging, facial recognition, and autonomous vehicles. In recent years, researchers in this field have presented many circuits, but they have many flaws in terms of speed, accuracy, and area consumption, and the need to create more efficient circuits is felt more than ever. Therefore, in this article, a new design for morphological operations and processing digital images is presented using QCA technology. This paper presents a new efficient QCA-based implementation of image processing based on the direct interactions between the QCA cells. This circuit uses two majority gates of five new inputs to produce the output and produces the desired output. In addition, a comparison and analysis of the area and clocking complexity, design cost, and energy dissipation through simulation using QCADesigner and QCADesigner-E are done. The results show that the presented circuit produces the expected and correct output results in 0.75 clock phases, and the obtained results show the high speed and low consumption space of the presented circuit. In addition, the presented circuit performs better than the previous best circuits in terms of quantum cost and delay, and according to the mentioned advantages, it can be used to improve and expand other circuits in image processing.

Design of ternary reversible Feynman and Toffoli gates in ternary quantum-dot cellular automata

The use of reversible logic gates leads to a reduction in energy loss in logic circuits by preventing information loss. New computing methods, such as quantum-dot cellular automata (QCA), have been offered by nanotechnology emerging with nanoelectronics to make more comprehensive logic circuits. In nanotechnology-based systems, some bits are erased when the system performs any computation, and this causes heat dissipation and energy loss in systems. Adder circuits are the basis of any arithmetic operation and one of the main parts of many circuits for creating complex hardware; therefore, the use of enhanced adder circuits leads to high performance in logic circuits. In irreversible logic, the energy that is transferred from the power supply to the circuit is converted into heat, and energy loss occurs. Power management plays a vital role in modern computational systems, and using ternary logic instead of previous technologies leads to better performance. The main purpose of our study is to design ternary quantum-dot cellular automata (TQCA) reversible logic gates based on ternary quantum-dot cellular technology. Reversible gates are the basis of creating a reversible circuit. In this paper, the Muthukrishnan-Stroud (M-S) gate, which is the basis of all other reversible ternary gates, is implemented in ternary QCA technology, and then, reversible ternary Feynman and Toffoli (C2NOT) gates are designed. More optimal adder circuits can be realized in three-valued technology using Feynman and Toffoli gates. The area, delay, and cell count of the proposed TQCA designs are compared with those of other related works, and the effect of fault on the designs in the presence of cell omission defect is determined. The occupied areas of the proposed Feynman and Toffoli gate designs are 0.069 μm2 and 0.073 μm2, respectively. Moreover, the fault tolerance levels of these TQCA gates are 77% and 92%, respectively.

Test generation algorithm for QCA circuits targeting novel defects and its corresponding fault models

Considering the scaling limitations of current Complementary Metal Oxide Semiconductor (CMOS) technology, Quantum-dot-Cellular Automata (QCA) is emerging as one of the alternatives. QCA being at the molecular scale, defects are more likely to occur in it. Therefore, substantial development of QCA-oriented defects, its corresponding fault models and test generation is required. In this paper, a test generation algorithm for a QCA combinational circuit is proposed. The FAN (A Fanout Oriented) test generation algorithm is extended for QCA. The proposed Automatic Test Pattern Generator (ATPG) for QCA targets Single Stuck at Fault (SSF) set produced by novel Multiple Missing Cells (MMC) defects. The proposed ATPG is based on the QCA-oriented test generation properties and guided by proposed testability measures.The MCNC benchmark circuits are synthesized into QCA using proposed synthesis algorithms to check the effectiveness of the proposed ATPG. The ATPG is developed using C++ and tested on MCNC benchmark circuits. Further, ATPG-generated test vectors are validated at the QCA device level to demonstrate their correctness. The QCADesigner-E tool is used for the device-level implementation of the MCNC benchmark circuit.

Reversible arithmetic and logic unit using a novel reversible NRRG gate in quantum dot technology

Quantum-dot Cellular Automata (QCA) has become one of the promising studies for nano-scale computing. QCA is one of the candidate technologies to be replaced with CMOS technology. QCA technology not only reduces power consumption and delay but also increases operating frequency and speed. The arithmetic logic unit is the essential component in a processor that performs arithmetic and logical operations. This paper presents a novel 5 × 5 reversible logic gate called the NRRG (Norouzi_Rasouli Reversible Gate) which can be used as the basic building block of 4:1 and 8:1 reversible multiplexers. Then, we have designed a RALU (reversible arithmetic and logic unit) using this gate. Our design can perform 20 operations such as AND, NAND, OR, XOR, XNOR, COPY, addition, and increment. The proposed QCA RALU requires 0.44 μm2 area, 480 QCA cells, and 10 clock phases. The proposed design needs less cell count, delay, and cost of QCA compared to previous works. The structure is implemented without any rotated cells and only uses one layer which improves the manufacturability of the design. The architectures are designed and simulated using QCA Designer 2.0.3.

An efficient new design of nano-scale comparator circuits using quantum-dot technology

Traditional semiconductor-based technology has recently faced many issues, such as physical scalability constraints and short-channel properties. Much research on nano-scale designs has resulted in these flaws. Quantum-dot Cellular Automata (QCA) is a promising nanotechnology solution for solving CMOS-related issues. The 4-dot squared cell is identified as the main feature of this technology. Also, a comparator is an essential electronic device that compares 2 voltages or currents. It is frequently employed to confirm whether an input has achieved a predefined value or not. So, the design of the QCA-based comparator is one of the interesting lines in recent studies. However, cell and area consumption limits the circuit design in the most relevant research. As a result, two efficient comparator circuits based on the inherent rules of quantum dots have been presented in this work. The proposed 1-bit design employs 35 quantum cells in a 0.04 μm2 compact layout space. Also, the proposed 2-bit design uses 173 cells in a 0.19 μm2 compact layout area. These circuits, which are built across three layers of 90-degree cells, remove the need for coplanar crossovers, ensuring accessible inputs and outputs. The presented 1-bit comparator circuit uses 3 majority gates with three inputs. The first output signal in 1-bit comparator is generated after 0.75 clock phases and in 2-bit design after 1.25 clock phases. QCADesigner-E evaluated the suggested circuits' practical accuracy, cost, and power. The results showed that the proposed designs are extremely efficient in cell and area consumption compared to the state-of-the-art designs.

High-performance binary to gray code converter: balancing energy use and thermal stability

Quantum Dot Cellular Automata (QCA) is an advanced technology in quantum electronics, leveraging quantum cells as its fundamental unit. This article introduces a design for a Binary to Gray (BG) code converter using the QCA technology. The proposed design uses fewer cells than previous models and extends the bit size capability to five bits in a single layer to minimize complexity and improve efficiency. The primary goal is to develop energy and thermal efficient BG code converters. These designs achieve a cell count reduction of 45.16% for two-bit, 29.54% for three-bit, and 25.45% for four-bit converters while improving the overall area by 41.17%, 29.54%, and 40% for two-bit,three-bit, and four-bit converters, respectively, with a latency of 0.5. The 55-cell, five-bit BG converter takes up 0.07μ m 2 and has a latency of 0.5. Comprehensive simulations were conducted using the QCADesigner, QCADesignerE 2.0.3, and QCA Pro tools to validate the proposed design’s functionality.

Energy efficient improved content addressable memory using quantum-dot cellular automata

Quantum-dot cellular automata (QCA) is an emerging technology with high integration density, low power consumption, and high operating speed. This study introduces a QCA-based modified content addressable memory (CAM) cell employing a five-input minority gate. The functionality, temperature sensitivity, and heat distribution of this modified CAM cell are comprehensively analyzed using QCADesigner E and QCA Pro simulation tools. The results reveal significant advancements over existing designs, with a remarkable 8.33% reduction in area and a substantial 63.7% decrease in energy consumption. Additionally, this modified CAM cell exhibits a notable 5% enhancement in temperature tolerance. These findings emphasize the QCA-based modified CAM cell is more efficient and thermally robust.

An ultra-low power QCA based vedic multiplier for digital radar application

Quantum-dot cellular automata (QCA) is a promising nanotechnology that appears to meet the requirements of high speed radar applications. Due to its advantages, including its extremely low power dissipation and less occupied area, it is highly regarded. The multiplier module is an essential component in Phased Array Radar (PAR). In the real-time PAR based systems, many applications like digital beam forming, local oscillators, and communication receivers etc. requires multiplication operation. However, the most important factors in these systems are the area and power consumption. This paper presents an ultra-low power vedic multiplier using QCA technology, and it provides the effective clocking, reduce the number of cells, and low energy dissipation. The 4×4 vedic multiplier utilizes only 2940 cells and occupies 7.33μm2 area with 7.64×10−1eV of energy dissipation. The total consumed power of this module is 1.61nW. This architecture outperforms complementary metal-oxide-semiconductor (CMOS) based circuits in terms of power by 90%. The proposed contribution will initiate a new direction of research into real-time PAR based systems.