Quantum-dot Cellular Automata Technology Research Articles

An Efficient Design of 2-BIT Arithmetic Logical Unit in Quantum Dot Cellular Automata

For the past two decades, CMOS technology has reigned supreme in the world of Very Large Scale Integration (VLSI). But Quantum Dot Cellular Automata (QCA) is stepping into the spotlight, offering a fresh solution to the growing challenges of CMOS. This paper delves into the potential of QCA circuits by presenting a 2-bit Arithmetic Logic Unit (ALU) crafted with this groundbreaking technology, while also benchmarking it against conventional CMOS designs. The proposed QCA-based ALU delivers a trifecta of benefits: streamlined circuit design, exceptional space efficiency, and reduced quantum cost—all while keeping performance sharp in terms of latency and area usage. This 2-bit ALU encompasses a suite of operations: addition, subtraction, multiplication, division, bitwise AND, OR, XOR, and XNOR. QCA technology addresses some of CMOS's major pain points, like slow switching speeds, and doesn't require additional power sources, making it both efficient and environmentally friendly. This is not just an incremental improvement; it's a bold leap into the future of circuit design

An Efficient Design of a Three-Layer Magnitude Comparator for Nano-Scale IoT Applications Based on QCA Technology

The difficulty of further downscaling CMOS technology arises from the restriction of feature size reduction. Quantum-dot cellular automata (QCA) emerges as a paradigm-shifting successor to CMOS, heralding a new era of effective digital design at the nanoscale. It stands as an enticing frontier in nanoscale computing, with limited exploration into the realms of smaller QCA cells, elevated processing speeds, and more compact area requirements across diverse circuits. Within the intricate landscape of decoding circuits and process controllers, the binary comparator assumes a role of paramount significance. On the other hand, the quickly developing Internet of Things (IoT) market aims to produce high-speed, low-power gadgets. A comparator is a crucial component in the analog-to-digital conversion process used by IoT devices. In order to meet the power and latency requirements of IoT devices, a high-speed, low-power comparator is greatly required. Consequently, the strategic design of comparators within the QCA framework has ascended to a position of heightened importance in cutting-edge research. This study undertakes the formidable task of conceiving QCA-centric designs for MV32, the majority gate, and the inverter gate, thereby contributing to the development of a sophisticated multi-layered comparator architecture for IoT devices. In the realization of a three-layer comparator implemented in QCA, we attain an impressive feat—a minimal clock zone demanding only a singular clock pulse coupled with exceptional compaction (measuring at a mere 0.03 μm2). Experimental revelations corroborate the substantial advancement of the proposed design over traditional methodologies, particularly in terms of circuit area, cell count, and clock efficiency.

Development of a high-performance arithmetic and logic unit for efficient digital signal processing based on reversible logic and quantum dots

Digital Signal Processing (DSP) finds a wide range of applications in various fields, including telecommunications, audio and video processing, biomedical engineering, radar systems, and image processing. Previous DSP designs faced limitations in available processing power and computational resources. Insufficient processing power could result in slower execution times, an inability to handle complex algorithms, or limited capacity to process high-speed or large-scale signals. As the demand for minimal power consumption in DSP circuits continues to grow, reversible logic and quantum-dot cellular automata (QCA) have emerged as promising technologies due to their inherent ability to reduce energy loss. Within this landscape, the arithmetic and logic unit (ALU) plays a vital role in complex circuitry, serving as a key component in digital signal processing applications. However, challenges persist, including high quantum cost and the need to limit the number of cells in the ALU design. To address these challenges, our research aims to develop an efficient ALU by integrating reversible logic and QCA technology. Our focus will be on generating essential components, such as Feynman gates, Fredkin gates, and full adder circuits, which serve as foundational building blocks for reversible logic and QCA designs. These components will be combined to construct a comprehensive ALU capable of performing 20 different operations. Our implementation efforts will be centered around QCADesigner, with a specific emphasis on digital signal processing systems that prioritize energy efficiency and optimal utilization of occupied areas.

Advancing nanoscale computing: Efficient reversible ALU in quantum-dot cellular automata

This paper presents a significant contribution to the field of nanoscale computing by proposing an innovative reversible Arithmetic and Logic Unit (ALU) implemented in Quantum-Dot Cellular Automata (QCA). Reversible logic and QCA technology offer promising alternatives to conventional CMOS technology, addressing the challenges of operating at nanoscale dimensions. The primary objective is to develop a highly efficient ALU capable of performing 26 distinct arithmetic and logical operations. The ALU design is based on a novel reversible full adder-subtractor optimized for minimal quantum cost, which is crucial for energy-efficient quantum computation. The evaluation encompasses various criteria related to reversibility, such as gate count, number of constant inputs, number of garbage outputs, and quantum cost. QCA-specific criteria, including cell count, occupied area, and clock cycles, are also considered. The outcomes of this research contribute to the advancement of cell-efficient nanoscale computing, with implications for quantum computation, emerging technologies, and future integrated circuit design.

Novel level and edge-triggered universal shift registers with low latency in QCA technology

Shift registers are one of the main blocks in processors. In this paper, two new universal shift registers are designed based on Quantum-Dot Cellular Automata (QCA) nanotechnology. Both of the proposed level triggered and edge triggered universal shift register in QCA technology shows good performance in regards of the number of cells, occupied area, delay, and power. These designs also have reset abilities. Simulations show that the proposed 4-bit level triggered universal shift register with reset ability has 1057 QCA cells, 1.27 μm2 occupied area, and delay of about three cycles of QCA clock. In addition, the proposed rising edge triggered 4-bit universal shift register with reset ability has 1085 QCA cells, 1.27 μm2 occupied area, and delay of about three cycles of QCA clocks.

Ultra-optimized demultiplexer unit design in quantum-dot cellular automata nanotechnology

Integrated circuit designers face challenges in using complementary metal oxide semiconductor (CMOS) technology as it has a large leakage current and scalability challenge in ultra-nanoscale regime. Quantum-dot Cellular Automata (QCA) is a nanotechnology that can replace CMOS for designing ultra-deep submicron circuits and overcoming CMOS limitations. In this research paper, a novel area-efficient 1:2 demultiplexer is proposed using QCA technology. A demultiplexer is an important combinational circuit used in communication systems and computer memories. It receives serial input data and routes data in parallel to multiple outputs. QCA Designer and QCA Pro-tools are used for layout, simulation, and analysis of power dissipation. 11 QCA cells are utilized in the construction of the proposed 1:2 demultiplexer. The cell area and layout cost of the proposed demultiplexer have improved to 42.11 % and 55.56 % of the current best design, respectively. An essential factor to consider when developing integrated circuits is power dissipation. The proposed design dissipates less power. The energy dissipation of the proposed design has improved to 57.67 % at the kink energy level of 1.5 of the current best design.

Comprehensive and Comparative Analysis of QCA-based Circuit Designs for Next-generation Computation

For the past several decades, VLSI design has been focused on lowering the size, power, and delay. As of now, this miniaturization does not seems to be a possible way to address the demands of consumers. Quantum Dot Cellular Automata (QCA) technology is a promising technique that is able to provide low-power high-speed circuits at nano-scale. Much work has been done in this area where the researchers have proposed a variety of combinational and sequential logic circuits for future computation. This article presents a concrete review of design approaches, logic circuits, clocking schemes, implementation tools, and possible fabrication methodologies presented so far in QCA technology. A critical comparative analysis is provided on the basis of reported performance parameters in the domain. The aim of this article is to collect all necessary information into a single source, highlight the research challenges to be taken in the near future, and enlighten the path for upcoming researchers in the area.

Enhancing fault tolerance in QCA-based RAM cells: A USE clock-driven approach with a novel majority voter

CMOS IC technology is encountering limitations due to fabrication challenges, matching characteristics, and the pursuit of miniaturization. These constraints have prompted the exploration of alternative technologies to cater to the demands of the nanoscale realm. Quantum Dot Cellular Automata (QCA) has emerged as a promising candidate for implementing digital systems at the nanoscale. However, given the nascent stage of QCA technology, the risk of defects during fabrication in the nano-regime is a significant concern. Consequently, the development of fault-tolerant circuits and systems becomes pivotal for the practical realization of this technology. In this study, we introduce a fault-tolerant 3-input majority voter (FT-MV3) designed to achieve 100% fault tolerance against single-cell omission and additional-cell defects. We also assess the fault tolerance of this design in the presence of other fabrication defects. Furthermore, our study includes an energy dissipation analysis of the proposed design. Additionally, we present layout designs for fault-tolerant RAM cells, both with and without the Universal, Scalable, and Efficient (USE) clocking scheme. Our findings demonstrate that the USE-based RAM cell design exhibits an impressive fault tolerance of 95.52% against single-cell omission defects, making it a robust choice for the implementation of reliable RAM architectures.

A new nano-design of 16-bit carry look-ahead adder based on quantum technology

There is a requirement and a desire to develop reliable and energy-efficient circuit designs that adapt to the expanding field of low-power circuit engineering in the VLSI domain based on nanotechnology. The quantum-dot cellular automata (QCA) technology possesses the potential to supplant the conventional, complementary metal-oxide-semiconductor (CMOS) technology in low-power nano-scale applications due to its diminutive cell dimensions, dependable circuitry architecture, and robust structural integrity. On the other hand, the carry look-ahead adder (CLA) is one of the vital circuits in digital processing utilized in diverse digital applications. In addition, for the design of this essential circuit, the occupied area and the delay play the primary role because using a simple formulation can reduce the occupied area, energy consumption, and the number of gates count. In the previous structures, high delay and use of traditional technology (like CMOS) caused an increase in the number of gate counts and occupied areas. Using QCA technology, simple quantum cells, and a low delay, all the previous shortcomings can be resolved to reduce the number of gate counts and low occupied area in the CLA circuit. This paper proposes a new method that helps the propagation characteristics generate suitable signals to reduce the number of gate counts based on adders in QCA technology. Several new blocks are used to design fast binary adders. Finally, an optimal four and 16-bit CLA circuit will be proposed based on the adder circuit. Furthermore, the execution and experimentation of outcomes are carried out utilizing QCADesigner-2.0.3. The simulation-based comparison of values justified the proposed design’s accuracy and efficiency. The simulation results demonstrate that the proposed circuit has a low area and quantum cell.

An ultra-dense and cost-efficient coplanar RAM cell design in quantum-dot cellular automata technology

An ultra-dense and cost-efficient coplanar RAM cell design in quantum-dot cellular automata technology

Efficient co-planar adder designs in quantum dot cellular automata: Energy and cost optimization with crossover elimination

Quantum dot cellular automata (QCA) stands as a highly promising nanotechnology, capable of outperforming conventional CMOS technology. Leveraging its advantages, this paper addresses the challenges in adder circuits related to size, delay, and cost by integrating QCA technology. A novel layout for a co-planar full adder in QCA is introduced, featuring a half-adder design with 23 cells in a single layer without any crossover, achieving a delay of 0.25 clock cycles. By utilizing inter-cellular effects inherent in QCA technology, the presented designs offer significant improvements in a variety of design metrics, and a cost efficiency of 64.3%, distinguishing them from traditional logic design approaches. Additionally, in order to ensure an efficient routing channel and a consistent structure of the adder design, a Universal, Scalable, and Efficient (USE) clocking scheme has also been employed. The adder design is further used to build 4-bit and 8-bit Ripple Carry Adders. An extensive study on energy dissipation using QCADesigner-E and QCAPro tools is conducted for three tunneling energies (0.5 Ek, 1 Ek, and 1.5 Ek). The full adder design showcases substantial improvement in energy to delay cost when compared to the closest reported design, achieving improvements of 91.66%, 89.03%, and 88% at 0.5 Ek, 1 Ek, and 1.5 Ek, respectively. The results highlight enhanced circuit efficiency and streamlined layouts, outperforming existing models and offering substantial benefits to high-performance and energy-efficient computing systems.

Designing an ultra-efficient Hamming code generator circuit for a secure nano-telecommunication network

Communication links forming secure telecommunications networks rely on various technologies such as message switching, circuit switching, or packet switching to transmit messages and data. Hamming codes, a family of linear error-correcting codes, are commonly used in communication networks to detect and correct one-bit and two-bit errors. However, reducing power consumption, occupied area, and latency in secure telecommunication networks remains a challenge for future information and communication technology. To address these challenges, emerging technologies like quantum dots offer potential solutions. Quantum-dot cellular automata (QCA) stands as a promising frontier in nanotechnology for enhancing secure telecommunications networks. It opens up the possibility of crafting high-performance, energy-efficient digital circuits. This research harnesses the potential of QCA and introduces groundbreaking innovations: a 3-8 decoder employing a single-layer layout and a 3-input XOR gate with a multi-layer configuration. These components are utilized in the design of an electronic circuit for Hamming codes, incorporating the QCA-based approach. It is important to note that practical implementation in real-world scenarios presents challenges due to the nature of QCA technology. As a result, the evaluation and validation of the proposed designs heavily rely on simulations using QCADesigner. While experimental validation in real-world scenarios is limited, the simulations provide insights into the functionality and feasibility of the suggested designs. By leveraging QCA, the proposed Hamming code circuit significantly enhances cell count, occupied area, and clock latency. The suggested design can be adapted to fit different generating matrices in Hamming codes without requiring drastic modifications to the underlying architecture.

An Efficient Design of a Parallel Prefix Adder based on QCA Technology

This paper presents an optimized Parallel Prefix Adders (PPA) based on Quantum dot Cellular Automata (QCA) technology. PPA presents the most used block in Arithmetic Logic Units (ALU) which presents a fundamental part in several digital integrated circuits. The classical implementation method of PPA based on traditional Complementary Metal Oxide Semiconductor (CMOS) Technology presents several problems in terms of frequency, power consumption, surface and others. The QCA technology offers several features such as ultralow power consumption, small size, and can operate up to 1 THz. In this work, a 4-bit Parallel Prefix Adder with a new prefix low area and high speed is proposed. The proposed design is based on a half-adder circuit and other logic gates. These designs were tested and simulated using the freely known QCA Designer Tool version 2.0.3. and QCA pro. The proposed Half-adder presents a reduction of 23% 46% and 36% in terms of cell count, latency and power consumption, respectively compared to existing designs. The proposed PPA design shows almost an optimization of 5% in area and 58% in latency compared to the RCA design. The proposed circuit present an optimization of 20% in term of energy consumption compared to the existing PPA 4-bit Brent Kung Adder design.

Elementary design and analysis of QCA-based T-flipflop for nanocomputing

Abstract This work presents a new T-flipflop design based on quantum-dot cellular automata technology, with the standard two inputs (T and clock) and two outputs (Q and Q̄). It adheres to the typical QCA layout design approach, which consists of two majority voters and one inverter (to produce the complementary output, Q̄). It is a single-layered design with no crossover. A memory loop is used to retain previous values and aid the toggling operation of the T-flipflop. This design achieves improved functionality and reduced area requirement compared to existing designs. In addition, the study investigated energy loss and cost functions. In particular, the total energy loss is reduced by 10% and 22% compared to the best design when analyzed with the QCAPro and QCADesigner-E (QDE) tools, respectively. The area-delay and energy-delay cost functions outperform the best current design by 1.3 and 1.07 times, respectively. Overall, this work advances QCA-based flipflop (QTFF) designs and emphasizes the potential of QCA technology for creating effective QCA circuits.

Design and simulation of Full-Subtractor based on Quantum-Dot cellular automata technology

A prospective replacement for CMOS technology is Quantum-dot Cellular Automata. It has advantages such as significant size reduction, fast switching speed, extremely high device density, and low energy usage. It is used to reduce the complexity of the digital circuit’ structure and to achieve a more efficient circuits. This paper focuses on the design of a Full-Subtractor. The number of cells used in the circuit structure is lowest because of the creativity in the design and the novel arrangement of quantum cells. As a result, the size of the circuit and the power loss have been reduced to a minimum compared to the circuits designed by the subtractor. The proposed structure is implemented in QCA technology as a single layer circuit. The suggested Full-Subtractor have been optimized in such a way that, compared to previous structures, has an improvement of 79.48% in cell number, 42.65% in delay, 48.65% in surface area and 68.96% in energy consumption. We utilize the QCADesigner and QCAPro tools to evaluate the performance of the proposed structure.

A unique universal block in QCA technology

The limitations of Complementary Metal Oxide Semiconductor (CMOS) such as high-power dissipation, short channel effects, and high lithography has prompted scientists to look forward to alternatives. Many nanotechnologies were emerged and still in the competition such as Fin Field-Effect Transistor (FinFET), Carbon Nanotube Field-Effect Transistor (CNFET), Quantum-dot Cellular Automata (QCA). QCA is a new nanoelectronics technology used a new method for calculations and it is a promising technology in terms of power dissipation. In QCA, circuit complexity is depending on cell count, area and latency. For commercial purposes a universal gate is necessary, this gate can be used alone to design any Boolean function, where in CMOS technology, the NAND or NOT gates have the ability to be a universal gate. The dominant gates in QCA are the majority gate with inverter where QCA circuits cannot be designed using only a universal gate. Because the structure of the gate is important in QCA, this paper introduces a new low complexity singular block that can be used as a universal block. The proposed block can be used to form AND, OR, NOT, Exclusive-OR (XOR) and Multiplexer (MUX). So, this block not just used to design any circuit but also it can be used to form other important functions XOR and MUX to build large circuits in an optimum form.

Towards nanoscale fault-tolerant logical circuits using proposed robust majority voter in quantum-dot cellular automata technology

The occupied area, power consumption, and delay are the most crucial and critical factors in constructing integrated circuits. Due to the reduced occupied area, highly low power consumption, and extremely high speed of quantum-dot cellular automata (QCA) technology, it is one of the finest alternatives to complementary metal–oxide–semiconductor (CMOS) technology for nanoscale construction of circuits. On the other hand, fault tolerance becomes crucial in QCA due to the inherent sensitivity of quantum dots to various sources of errors and faults. These errors can arise from environmental disturbances, manufacturing imperfections, thermal fluctuations, and other factors. The presence of defects or faults can significantly impact the functionality and accuracy of QCA systems, leading to incorrect computation or signal corruption. To address these challenges, fault-tolerant structures are designed in QCA systems. These structures are specifically engineered to detect, tolerate, and mitigate the effects of faults, thereby enhancing the reliability and robustness of QCA-based computation. Fault-tolerant designs aim to ensure that the system can continue to operate correctly even in the presence of defects or faults. In QCA, proposed a fault-tolerant majority gate is necessary to ensure reliable computation in the presence of defects or faults. The fault-tolerant majority gate is a fundamental component in digital logic circuits, and it plays a crucial role in performing computations. It takes multiple input signals and produces an output based on the majority of those inputs. In classical computing, the majority gates are typically implemented using transistors. Therefore, this paper introduces a new and efficient fault-tolerant 3-input majority voter (FT MV3) using 11 simple and rotated cells in the QCA technology, which is 100% and 90.47% tolerant against single-cell and double-cell omission defects. The recommended FT MV3 gate verification is confirmed using some physical proofs. Afterward, to illustrate the performance of the introduced gate, three fault-tolerant computational circuits, including multiplexer, adder and ALU, are presented using the introduced FT MV3 gate. The comparison of the proposed fault tolerant ALU to the best coplanar design shows a 28.80% and 34.01% reduction of cell count and occupied area, respectively. All circuits are simulated using QCADesigner 2.0.3 software.

Flip Flops Design in Quantum Dot Cellular Automata Technology: Towards Digitization

Quantum-Dot Cellular Automata (QCA) is a transistor-less technology. In QCA, Columbic repulsion between electrons in the quantum dots makes data transfer possible. This paper presents the design of flip flops using a proposed Rotated-Normal Cells with Displacement (RND) inverter and a cell interaction method. The SR latch, SR Flip Flop (FF), D FF, and T FF are developed using QCA. The proposed D FF gives total and average energy dissipation of 1.31e-002eV and 1.19e-003eV respectively. It also gives a delay of 1 clock phase. The Proposed T FF provides total and average energy dissipation of 2.40e-002eV and 2.18e-003eV respectively, depicting efficient D FF and T FF in energy dissipation. The proposed SR Flip flop design gives an efficient area. The FFs with the proposed RND inverter and cell interaction method can be the best choice for future Nano communication to construct Nano circuits with less energy dissipation and high speed.

Design of BCD Adder Using QCA Technology

Abstract: Quantum-dot Cellular Automata (QCA) technology is a promising alternative to traditional complementary metaloxide-semiconductor (CMOS) technology for implementing digital circuits due to its potential for high speed, low power consumption, and small size. In this paper, we present a design for a Binary Coded Decimal (BCD) adder using QCA technology. The BCD adder is a crucial building block for arithmetic operations in decimal representation. The proposed design uses QCA cells to perform the addition operation of two BCD digits, which are encoded as a 4-bit binary number. The design includes a full-adder circuit, a BCD-to-binary converter, and a carry-lookahead adder. Simulation results using QCA Designer software demonstrate the functionality and feasibility of the proposed BCD adder design. The proposed design provides a promising alternative to traditional CMOS-based BCD adders and can contribute to the development of QCA-based digital circuits

A quantum-based building block for designing a nanoscale full adder circuit with power analysis

Quantum-dot cellular automata (QCA) concentrates charges using the Coulomb interaction. Despite the nanometric scale and the extremely high projected working frequency, the need for transmission is eliminated, resulting in very low power consumption. Few designs exist to reduce energy consumption and provide simple access to inputs and outputs. There have been few studies on the optimizations of majority and inverter gates for different types of adders. The design of adders using a QCA framework is becoming more significant in current research. This work aims to design a multi-layered full adder architecture that uses three-input XOR and a majority gate for the QCA framework. The primary goal of this article is to design a circuit with low power consumption and easy access to inputs and outputs. For a full adder by the QCA technology, a minimum clock zone of two clocks and 18 QCA cells by high compaction (0.02 μm2) are obtained. Additionally, the synthesis of high-level logic establishes the design's utility. In comparison to traditional design methodologies, experimental results show considerable design level gains in terms of circuit area, cell count, power, and clock. Experiments show how the design level has significantly improved compared to traditional design methodologies regarding circuit area, cell count, power, and clock.