Quantum-dot Cellular Automata Technology Research Articles

Area-delay efficient BCD adder in quantum dot cellular automata

Abstract Quantum-dot Cellular Automata (QCA) technology presents a promising avenue for the realization of ultralow-power and high-speed digital circuits owing to its inherent quantum properties and nanoscale dimensions. In this study, a novel design and analysis of a binary-coded decimal (BCD) adder implemented using QCA technology is proposed. The BCD adder is a fundamental component of digital arithmetic circuits and is widely applied in various computational systems, including calculators, processors, and digital signal processors. Leveraging the unique features of QCA, such as the absence of current flow and the potential for highly compact layouts, we present a detailed design methodology for the BCD adder circuit, including the implementation of basic QCA gates and construction of the BCD addition logic. Performance metrics, such as area, delay, and power consumption, were evaluated through extensive simulations using QCA Designer, QCA design, and a simulation tool. The Ripple Carry Adder (RCA) is one of the major blocks in the BCD circuit and a prominent factor in determining the area and delay of the circuit. Therefore, an efficient full adder was used to design an RCA with less area and delay. Clocking in a QCA impacts the polarization state of a QCA cell, and this scheme is utilized efficiently to achieve novelty. The proposed design occupies 15.625% less area, and the cell count is reduced by 11.55% compared with the existing state-of-the-art design. Power dissipation reports were obtained using the QCA Pro tool, which briefly describes the average leakage and average dissipation energy of the total circuit, and a spectrum to depict the energy dissipation of each cell in the circuit. The results demonstrate the feasibility and efficiency of the proposed BCD adder design in QCA technology, demonstrating its potential for realizing energy-efficient and high-performance digital arithmetic circuits. This work contributes to the growing body of research on QCA-based digital circuit design and lays the groundwork for the further exploration of QCA technology in practical computing applications.

Pseudo random bit generator in QCA for high speed communications

Quantum-dot cellular automata (QCA) technology is another new technology in the field of nanoelectronics and quantum. With the help of this technology, basic to advanced digital circuits can be designed and implemented with low energy consumption and small area. Therefore, in this paper, a new design for a four- and eight-bit Linear feedback shift register (LFSR) or random counter, as well as a rising-edge-sensitive D flip-flop with the least possible number of cells and the smallest area, was presented. This paper first designs the proposed D flip-flop with 24 cells and an area of 0.01μm2, so that with the help of this flip-flop it can design four and eight-bit LFSR. This flip-flop is one of the most optimal and suitable designs in terms of area and number of cells. Then, in the second step, a four-bit LFSR with 144 cells and an area of 0.2μm2 was designed with the help of the proposed flip-flop in the most optimal possible state. Also, in the third step, an eight-bit LFSR with 281 cells and an area of 0.4μm2 has been implemented for the first time in QCA technology, which is among the best possible designs. All the designs and simulations of this article were done in QCADesigner version 2.0.3 software and with QCAPro software, the energy consumption of the proposed circuits.

Reliable Synchronous and Asynchronous Counter Design in QCA

Due to rapid growth in the integrated circuit (IC) industry, the demand for compact digital system design is high. However, the continued technology reductions made the feasibility of further scaling down transistor size more challenging. In response to the growing demand for ultra-compact IC designs, the revolutionary quantum-dot cellular automata (QCA) technology has emerged as a promising solution. In a digital era, the counters are widely adopted in the peer-to-peer process flow to establish a mechanism for generating unique values for each identifier/number. In this work, a unique synchronous and asynchronous counters architecture is proposed with a reliable D and T flip-flop design. The proposed QCA architecture is implemented and validated with the QCA designer tool. Furthermore, in QCA technology, unreliable QCA designs can lead to frequent errors and malfunctions in the implemented logic. To overcome this challenge, the proposed design prioritizes cell placement (the relative positions of QCA cells) to make the circuit more robust. As a result, the circuit can still produce the expected functionality even if some QCA cells malfunction. Hence, to ensure the reliability of the proposed QCA architecture, the missing cell defect analysis is carried out in comparison with existing state-of-the-art designs. Based on comparison results, the unique designs like the proposed multiplexer, D flip-flop and T flip-flop design exhibit success rates of 67.28, 77.04 and 85.15%, respectively. The experimental results demonstrate that the proposed counter-architecture outperforms existing architectures.

Three different topologies for 4-bit counters in quantum-dot cellular automata technology

Abstract QCA (Quantum-dot Cellular Automata) technology is an innovative technology based on quantum principles and uses quantum dots as the basic units for information transfer. This technology enables the fabrication of electronic circuits at high speed, lower power consumption and smaller size. For this reason, in this article, for the first time, three types of counters are designed in QCA technology with the least cell and the smallest area. First, Johnson ring counter with 132 cells, area of 0.16 μ m 2 and a delay of 2 clock cycles, then synchronous counter with 192 cells and area of 0.2 μ m 2 and finally synchronous with reset capability with 267 cells and area of ​ 0.27 μ m 2 is designed. Also, the number of cells and the occupied area of the proposed designs have improved by 25.82 % and 35 % , respectively, compared to different authorities. As a result, the proposed designs are among the most optimal designs among different authorities. All the simulations were done in QCAPro and QCADesigner version 2.0.3 softwares.

Design of SRAM cell using an optimized D-latch in quantum-dot cellular automata (QCA) technology

A newer nanoscale technology called quantum-dot cellular automata (QCA) has been used by researchers to design digital circuits in place of the more traditional complementary metal–oxide semiconductor (CMOS) technology. This recent development in the technology change is due to the problems faced by CMOS technology in terms of power consumption and physical limitations. The advantages of QCA technology over CMOS technology are high density, low power consumption, high-speed operation, and less footprint area. This research provides a novel circuit for D-latch and static random access memory (SRAM) cells based on QCA technology. Initially, a D-latch circuit is proposed with a layout area of 0.01 μm2, a 0.5 clock cycle delay (latency), and a cell count of 18 QCA cells. Furthermore, an SRAM cell is proposed using the same D-latch circuit, which uses cell counts of 26 QCA cells and contributes to a layout area of 0.02 μm2 with a 0.75 clock cycle delay (latency). It is observed that our proposed circuits have a smaller layout area, fewer QCA cell counts, and a lower clock cycle delay (latency) than existing circuits.

Design of ternary reversible Feynman and Toffoli gates in ternary quantum-dot cellular automata

The use of reversible logic gates leads to a reduction in energy loss in logic circuits by preventing information loss. New computing methods, such as quantum-dot cellular automata (QCA), have been offered by nanotechnology emerging with nanoelectronics to make more comprehensive logic circuits. In nanotechnology-based systems, some bits are erased when the system performs any computation, and this causes heat dissipation and energy loss in systems. Adder circuits are the basis of any arithmetic operation and one of the main parts of many circuits for creating complex hardware; therefore, the use of enhanced adder circuits leads to high performance in logic circuits. In irreversible logic, the energy that is transferred from the power supply to the circuit is converted into heat, and energy loss occurs. Power management plays a vital role in modern computational systems, and using ternary logic instead of previous technologies leads to better performance. The main purpose of our study is to design ternary quantum-dot cellular automata (TQCA) reversible logic gates based on ternary quantum-dot cellular technology. Reversible gates are the basis of creating a reversible circuit. In this paper, the Muthukrishnan-Stroud (M-S) gate, which is the basis of all other reversible ternary gates, is implemented in ternary QCA technology, and then, reversible ternary Feynman and Toffoli (C2NOT) gates are designed. More optimal adder circuits can be realized in three-valued technology using Feynman and Toffoli gates. The area, delay, and cell count of the proposed TQCA designs are compared with those of other related works, and the effect of fault on the designs in the presence of cell omission defect is determined. The occupied areas of the proposed Feynman and Toffoli gate designs are 0.069 μm2 and 0.073 μm2, respectively. Moreover, the fault tolerance levels of these TQCA gates are 77% and 92%, respectively.

An efficient nano-design of image processor circuits for morphology operations based on quantum dots

Quantum-dot cellular automata (QCA) are one of the most promising alternatives to traditional VLSI technology despite significant current obstacles. The QCA has the advantages of very low power dissipation, faster switching speed, and extremely low circuit area, which can be used in designing nano-scale image processing circuits. Morphological operations and processing of digital image processing is a significant topic for researchers because it is widely used for analyzing, enhancing, and modifying images to extract meaningful information or improve their visual quality. Image processing is also used for image retrieval and enhancement, image compression, object recognition, machine vision, and medical applications. QCA technology, as a new and leading technology with great potential, can play a fundamental role in morphological operations, processing digital images, image editing, medical imaging, facial recognition, and autonomous vehicles. In recent years, researchers in this field have presented many circuits, but they have many flaws in terms of speed, accuracy, and area consumption, and the need to create more efficient circuits is felt more than ever. Therefore, in this article, a new design for morphological operations and processing digital images is presented using QCA technology. This paper presents a new efficient QCA-based implementation of image processing based on the direct interactions between the QCA cells. This circuit uses two majority gates of five new inputs to produce the output and produces the desired output. In addition, a comparison and analysis of the area and clocking complexity, design cost, and energy dissipation through simulation using QCADesigner and QCADesigner-E are done. The results show that the presented circuit produces the expected and correct output results in 0.75 clock phases, and the obtained results show the high speed and low consumption space of the presented circuit. In addition, the presented circuit performs better than the previous best circuits in terms of quantum cost and delay, and according to the mentioned advantages, it can be used to improve and expand other circuits in image processing.

Reversible arithmetic and logic unit using a novel reversible NRRG gate in quantum dot technology

Quantum-dot Cellular Automata (QCA) has become one of the promising studies for nano-scale computing. QCA is one of the candidate technologies to be replaced with CMOS technology. QCA technology not only reduces power consumption and delay but also increases operating frequency and speed. The arithmetic logic unit is the essential component in a processor that performs arithmetic and logical operations. This paper presents a novel 5 × 5 reversible logic gate called the NRRG (Norouzi_Rasouli Reversible Gate) which can be used as the basic building block of 4:1 and 8:1 reversible multiplexers. Then, we have designed a RALU (reversible arithmetic and logic unit) using this gate. Our design can perform 20 operations such as AND, NAND, OR, XOR, XNOR, COPY, addition, and increment. The proposed QCA RALU requires 0.44 μm2 area, 480 QCA cells, and 10 clock phases. The proposed design needs less cell count, delay, and cost of QCA compared to previous works. The structure is implemented without any rotated cells and only uses one layer which improves the manufacturability of the design. The architectures are designed and simulated using QCA Designer 2.0.3.

High-performance binary to gray code converter: balancing energy use and thermal stability

Quantum Dot Cellular Automata (QCA) is an advanced technology in quantum electronics, leveraging quantum cells as its fundamental unit. This article introduces a design for a Binary to Gray (BG) code converter using the QCA technology. The proposed design uses fewer cells than previous models and extends the bit size capability to five bits in a single layer to minimize complexity and improve efficiency. The primary goal is to develop energy and thermal efficient BG code converters. These designs achieve a cell count reduction of 45.16% for two-bit, 29.54% for three-bit, and 25.45% for four-bit converters while improving the overall area by 41.17%, 29.54%, and 40% for two-bit,three-bit, and four-bit converters, respectively, with a latency of 0.5. The 55-cell, five-bit BG converter takes up 0.07μ m 2 and has a latency of 0.5. Comprehensive simulations were conducted using the QCADesigner, QCADesignerE 2.0.3, and QCA Pro tools to validate the proposed design’s functionality.

An ultra-low power QCA based vedic multiplier for digital radar application

Quantum-dot cellular automata (QCA) is a promising nanotechnology that appears to meet the requirements of high speed radar applications. Due to its advantages, including its extremely low power dissipation and less occupied area, it is highly regarded. The multiplier module is an essential component in Phased Array Radar (PAR). In the real-time PAR based systems, many applications like digital beam forming, local oscillators, and communication receivers etc. requires multiplication operation. However, the most important factors in these systems are the area and power consumption. This paper presents an ultra-low power vedic multiplier using QCA technology, and it provides the effective clocking, reduce the number of cells, and low energy dissipation. The 4×4 vedic multiplier utilizes only 2940 cells and occupies 7.33μm2 area with 7.64×10−1eV of energy dissipation. The total consumed power of this module is 1.61nW. This architecture outperforms complementary metal-oxide-semiconductor (CMOS) based circuits in terms of power by 90%. The proposed contribution will initiate a new direction of research into real-time PAR based systems.

Hybrid Quantum-Dot Cellular Automata Nanocomputing Circuits

Quantum-dot cellular automata (QCA) is an emerging transistor-less field-coupled nanocomputing (FCN) approach to ultra-scale ‘nanochip’ integration. In QCA, to represent digital circuitry, electrostatic repulsion between electrons and the mechanism of electron tunnelling in quantum dots are used. QCA technology can surpass conventional complementary metal oxide semiconductor (CMOS) technology in terms of clock speed, reduced occupied chip area, and energy efficiency. To develop QCA circuits, irreversible majority gates are typically used as the primary components. Recently, some studies have introduced reversible design techniques, using reversible majority gates as the main building block, to develop ultra-energy-efficient QCA circuits. However, this approach resulted in time delays, an increase in the number of QCA cells used, and an increase in the chip area occupied. This work introduces a novel hybrid design strategy employing irreversible, reversible, and partially reversible QCA gates to establish an optimal balance between power consumption, delay time, and occupied area. This hybrid technique allows the designer to have more control over the circuit characteristics to meet different system needs. A combination of reversible, irreversible, and innovative partially reversible majority gates is used in the proposed hybrid design method. We evaluated the hybrid design method by examining the half-adder circuit as a case study. We developed four hybrid QCA half-adder circuits, each of which simultaneously incorporates various types of majority gates. The QCADesigner-E 2.2 simulation tool was used to simulate the performance and energy efficiency of the half-adders. This tool provides numerical results for the circuit input/output response and heat dissipation at the physical level within a microscopic quantum mechanical model.

Efficient Design and Implementation of QCA SISO Shift Register Circuits for Nanocomputing

The most promising emerging technology that can reduce the power, area and delay in digital circuits is Quantum-dot Cellular Automata (QCA) technology. The Serial Input-Serial Output (SISO) Shift Register (SR) is a basic component in digital circuits. The SISO SR can be designed using two methods in the QCA technology, directly mapping circuits from the CMOS technology and using the inherent capability of the QCA technology. This paper presents and evaluates the new [Formula: see text]-bit QCA SISO SR that not only uses the inherent capability of QCA technology but also has a regular architecture. The proposed [Formula: see text]-bit SISO SR is developed based on the building block, which is designed in this paper. In addition, the developed QCA SISO SR has coplanar architecture and it has the ability to correct or change data. The proposed [Formula: see text]-bit SISO SR is evaluated for 3, 4 and 5 bits using QCADesigner-[Formula: see text]. The results demonstrate that the designed circuits for 3-, 4- and 5-bit QCA SISO SRs require 68 (0.06 [Formula: see text]m[Formula: see text], 92 (0.08[Formula: see text][Formula: see text]m[Formula: see text] and 116 (0.09[Formula: see text][Formula: see text]m[Formula: see text] cells (area), respectively. The comparison demonstrates that the developed QCA SISO SRs have advantages in comparison to other QCA SISO SR circuits.

Design and simulation of a new QCA-based low-power universal gate

Quantum-dot Cellular Automata (QCA) is recognized in electronics for its low power consumption and high-density capabilities, emerging as a potential substitute for CMOS technology. GDI (Gate Diffusion Input) technology is featured as an innovative approach for enhancing power efficiency and spatial optimization in digital circuits. This study introduces an advanced four-input Improved Gate Diffusion Input (IGDI) design specifically for QCA technology as a universal gate. A key feature of the proposed 10-cell block is the absence of cross-wiring, which significantly enhances the circuit’s operational efficiency. Its universal cell nature allows for the carrying out of various logical gates by merely altering input values, without necessitating any structural redesign. The proposed design showcases notable advancements over prior models, including a reduced cell count by 17%, a 29% decrease in total energy usage, and a 44% reduction in average energy loss. This innovative IGDI design efficiently executes 21 combinational and various sequential functions. Simulations in 18 nm technology, accompanied by energy consumption analyses, demonstrate this design’s superior performance compared to existing models in key areas such as multiplexers, comparators, and memory circuits, alongside a significant reduction in cell count.

An Efficient Design of 2-BIT Arithmetic Logical Unit in Quantum Dot Cellular Automata

For the past two decades, CMOS technology has reigned supreme in the world of Very Large Scale Integration (VLSI). But Quantum Dot Cellular Automata (QCA) is stepping into the spotlight, offering a fresh solution to the growing challenges of CMOS. This paper delves into the potential of QCA circuits by presenting a 2-bit Arithmetic Logic Unit (ALU) crafted with this groundbreaking technology, while also benchmarking it against conventional CMOS designs. The proposed QCA-based ALU delivers a trifecta of benefits: streamlined circuit design, exceptional space efficiency, and reduced quantum cost—all while keeping performance sharp in terms of latency and area usage. This 2-bit ALU encompasses a suite of operations: addition, subtraction, multiplication, division, bitwise AND, OR, XOR, and XNOR. QCA technology addresses some of CMOS's major pain points, like slow switching speeds, and doesn't require additional power sources, making it both efficient and environmentally friendly. This is not just an incremental improvement; it's a bold leap into the future of circuit design

An Efficient Design of a Three-Layer Magnitude Comparator for Nano-Scale IoT Applications Based on QCA Technology

The difficulty of further downscaling CMOS technology arises from the restriction of feature size reduction. Quantum-dot cellular automata (QCA) emerges as a paradigm-shifting successor to CMOS, heralding a new era of effective digital design at the nanoscale. It stands as an enticing frontier in nanoscale computing, with limited exploration into the realms of smaller QCA cells, elevated processing speeds, and more compact area requirements across diverse circuits. Within the intricate landscape of decoding circuits and process controllers, the binary comparator assumes a role of paramount significance. On the other hand, the quickly developing Internet of Things (IoT) market aims to produce high-speed, low-power gadgets. A comparator is a crucial component in the analog-to-digital conversion process used by IoT devices. In order to meet the power and latency requirements of IoT devices, a high-speed, low-power comparator is greatly required. Consequently, the strategic design of comparators within the QCA framework has ascended to a position of heightened importance in cutting-edge research. This study undertakes the formidable task of conceiving QCA-centric designs for MV32, the majority gate, and the inverter gate, thereby contributing to the development of a sophisticated multi-layered comparator architecture for IoT devices. In the realization of a three-layer comparator implemented in QCA, we attain an impressive feat—a minimal clock zone demanding only a singular clock pulse coupled with exceptional compaction (measuring at a mere 0.03 μm2). Experimental revelations corroborate the substantial advancement of the proposed design over traditional methodologies, particularly in terms of circuit area, cell count, and clock efficiency.

Development of a high-performance arithmetic and logic unit for efficient digital signal processing based on reversible logic and quantum dots

Digital Signal Processing (DSP) finds a wide range of applications in various fields, including telecommunications, audio and video processing, biomedical engineering, radar systems, and image processing. Previous DSP designs faced limitations in available processing power and computational resources. Insufficient processing power could result in slower execution times, an inability to handle complex algorithms, or limited capacity to process high-speed or large-scale signals. As the demand for minimal power consumption in DSP circuits continues to grow, reversible logic and quantum-dot cellular automata (QCA) have emerged as promising technologies due to their inherent ability to reduce energy loss. Within this landscape, the arithmetic and logic unit (ALU) plays a vital role in complex circuitry, serving as a key component in digital signal processing applications. However, challenges persist, including high quantum cost and the need to limit the number of cells in the ALU design. To address these challenges, our research aims to develop an efficient ALU by integrating reversible logic and QCA technology. Our focus will be on generating essential components, such as Feynman gates, Fredkin gates, and full adder circuits, which serve as foundational building blocks for reversible logic and QCA designs. These components will be combined to construct a comprehensive ALU capable of performing 20 different operations. Our implementation efforts will be centered around QCADesigner, with a specific emphasis on digital signal processing systems that prioritize energy efficiency and optimal utilization of occupied areas.

Advancing nanoscale computing: Efficient reversible ALU in quantum-dot cellular automata

This paper presents a significant contribution to the field of nanoscale computing by proposing an innovative reversible Arithmetic and Logic Unit (ALU) implemented in Quantum-Dot Cellular Automata (QCA). Reversible logic and QCA technology offer promising alternatives to conventional CMOS technology, addressing the challenges of operating at nanoscale dimensions. The primary objective is to develop a highly efficient ALU capable of performing 26 distinct arithmetic and logical operations. The ALU design is based on a novel reversible full adder-subtractor optimized for minimal quantum cost, which is crucial for energy-efficient quantum computation. The evaluation encompasses various criteria related to reversibility, such as gate count, number of constant inputs, number of garbage outputs, and quantum cost. QCA-specific criteria, including cell count, occupied area, and clock cycles, are also considered. The outcomes of this research contribute to the advancement of cell-efficient nanoscale computing, with implications for quantum computation, emerging technologies, and future integrated circuit design.

Novel level and edge-triggered universal shift registers with low latency in QCA technology

Shift registers are one of the main blocks in processors. In this paper, two new universal shift registers are designed based on Quantum-Dot Cellular Automata (QCA) nanotechnology. Both of the proposed level triggered and edge triggered universal shift register in QCA technology shows good performance in regards of the number of cells, occupied area, delay, and power. These designs also have reset abilities. Simulations show that the proposed 4-bit level triggered universal shift register with reset ability has 1057 QCA cells, 1.27 μm2 occupied area, and delay of about three cycles of QCA clock. In addition, the proposed rising edge triggered 4-bit universal shift register with reset ability has 1085 QCA cells, 1.27 μm2 occupied area, and delay of about three cycles of QCA clocks.

Ultra-optimized demultiplexer unit design in quantum-dot cellular automata nanotechnology

Integrated circuit designers face challenges in using complementary metal oxide semiconductor (CMOS) technology as it has a large leakage current and scalability challenge in ultra-nanoscale regime. Quantum-dot Cellular Automata (QCA) is a nanotechnology that can replace CMOS for designing ultra-deep submicron circuits and overcoming CMOS limitations. In this research paper, a novel area-efficient 1:2 demultiplexer is proposed using QCA technology. A demultiplexer is an important combinational circuit used in communication systems and computer memories. It receives serial input data and routes data in parallel to multiple outputs. QCA Designer and QCA Pro-tools are used for layout, simulation, and analysis of power dissipation. 11 QCA cells are utilized in the construction of the proposed 1:2 demultiplexer. The cell area and layout cost of the proposed demultiplexer have improved to 42.11 % and 55.56 % of the current best design, respectively. An essential factor to consider when developing integrated circuits is power dissipation. The proposed design dissipates less power. The energy dissipation of the proposed design has improved to 57.67 % at the kink energy level of 1.5 of the current best design.

Comprehensive and Comparative Analysis of QCA-based Circuit Designs for Next-generation Computation

For the past several decades, VLSI design has been focused on lowering the size, power, and delay. As of now, this miniaturization does not seems to be a possible way to address the demands of consumers. Quantum Dot Cellular Automata (QCA) technology is a promising technique that is able to provide low-power high-speed circuits at nano-scale. Much work has been done in this area where the researchers have proposed a variety of combinational and sequential logic circuits for future computation. This article presents a concrete review of design approaches, logic circuits, clocking schemes, implementation tools, and possible fabrication methodologies presented so far in QCA technology. A critical comparative analysis is provided on the basis of reported performance parameters in the domain. The aim of this article is to collect all necessary information into a single source, highlight the research challenges to be taken in the near future, and enlighten the path for upcoming researchers in the area.