Quantum-dot Cellular Automata Layout Research Articles

Quantum‐dot cellular automata based design for overflow detection in two's complement arithmetic operation

AbstractThis article describes designing a low‐power novel circuit for overflow detection in two's complement arithmetic operations. The quantum‐dot cellular automata (QCA) is employed to achieve the nanoscale design. For designing the circuit of the proposed arithmetic overflow detector, a new layout of the QCA full adder is utilized. Two different designs of arithmetic overflow detectors are outlined in this article. The designs are compared based on latency, cell count, and device area. Based on the comparison, the best design for an arithmetic overflow detector is presented. The circuit cost for all the designs is also shown in this work. Besides, thermal power's effect on the output cell's polarization has also been investigated. The power dissipation of all proposed QCA layouts is estimated.

Framework for QCA Layout Generation and Rules for Rotated Cell Design

Quantum-dot Cellular Automata (QCA) is a nontransistor-based nanotechnology circuit design paradigm. The circuits are implemented by using cells having quantum dots and electrons. There are several cell configurations with varying combinations of electrons and quantum dots. But the widely used cells have the four-dot two-electron structure. Circuits are realized and validated by using QCADesigner. However, the layouts are developed manually by using this tool. Layouts are not entirely automated in QCA. Hence, in this work, the existing QCA tools and the different techniques proposed in the literature to improve the QCA layout generation are analyzed and a complete framework for QCA layout generation is proposed. It also explores the gap that needs to be filled to achieve a reliable CAD tool for QCA layout generation. In addition to that, to design circuits using rotated cells, design rules and cost functions are proposed. Novel circuits of multiplexer and D-flip-flop are also proposed using rotated cells. The proposed designs have better output polarization compared to other designs. Verification is done in QCADesigner.

Single layer adder/subtractor using QCA nanotechnology for nanocomputing operations

Quantum-dot cellular automata (QCA) nanotechnology is a suitable replacement for the widely accepted complementary metal oxide semiconductor (CMOS) technology. CMOS technology faces the issues of high-leakage current and non-scalability in the ultra-deep submicron (ultra-DSM) regime. It motivates the researchers to explore new technologies for further advancement of the field. QCA nanotechnology is energy-efficient technology and it overcomes the issues of CMOS technology in ultra-DSM regime. In this paper, a novel 3-input XOR structure is presented using QCA nanotechnology. The full adder and the full subtractor circuits based on the 3-input XOR gate are developed. A circuit for the full adder/subtractor nanostructure is proposed in the paper. All the proposed designs are optimal, fault-tolerant and single-layered. The proposed full adder contains only 21 QCA cells, while 22 QCA cells are required for the proposed full subtractor. The proposed full adder/subtractor structure consists of only 30 QCA cells. The proposed designs are compared with the existing designs for the number of QCA cells, total cell area, total covered area, area utilization, clock latency, QCA layout cost, and crossover requirement. The energy-efficient behaviour of the proposed circuits is calculated using the QCA Designer-E and the QCA Pro tools.

Design and Analysis of Novel Non-Reversible & Reversible Parity Generator and Detector in Quantum Cellular Automata using Feynman Gate

Aim: A novel design for non-reversible as well as reversible parity generator and detector in Quantum-dot Cellular Automata (QCA) technology is presented in this research article. Parity generator and detector circuits are reliable error-checking components of a nano-communication system. Objective: The main focus of this research is to design an ultra-low-power fault-tolerant reversible gate implementation of the parity logic function in QCA. An efficient QCA design layout with minimal area, less latency and the least energy dissipation is desired. Methods: The proposed designs are developed using Quantum-dot Cellular Automata (QCA) technology. The circuits are optimized using majority gate reduction and clock zone reduction techniques. Also, the cell-cell interaction technique is employed to further optimize the QCA circuit. To increase the fault tolerance and ultra-low power operation, reversible QCA circuits are designed using cascaded Feynman gates. Results Conclusion: The efficiency of the parity generator and detector is calculated to be more than 25% compared to existing QCA layouts. It is demonstrated in this paper that the proposed circuits perform exceptionally well on every design parameter. The design parameters under consideration are cell count, cell area, complexity, crossover count, latency and energy dissipation. Conclusion: Using reversible logic, a fault-tolerant and defect-sensitive circuit are developed for parity generation and detection.

Majority logic based area-delay efficient 1-bit approximate adder for error-tolerant applications

The complementary metal oxide semiconductor (CMOS) technology is approaching its physical limits due to lithographic issues and diminishing benefits of scaling. The new technologies such as quantum dot cellular automata (QCA), tunneling phase logic (TPL), nonmagnetic logic (NML), single electron tunneling (SET), etc are emerging as an alternative and may supersede the conventional CMOS technologies in the near future. Now days, the design of approximate computing based on QCA technologies has gaining much of recent interest. In this paper, a majority-logic (ML) based area-delay efficient novel approximate full adder (AFA) is presented. The QCA layout of proposed AFA is designed and simulated using QCADesigner tool. Further, the proposed AFA is analyzed and compared against the state-of-the-art approximate adders referred to as ‘reported AFAs’ (RAAs), in terms of error metrics (EMs), area, and time complexity. Also, analyzed its efficacy for error-tolerant applications such as image processing.

Towards the Design and Analysis of Multiplexer/Demultiplexer Using Quantum Dot Cellular Automata for Nano Systems

Quantum dot Cellular Automata (QCA) is a rapidly developing nanotechnology that offersultra-low energy loss, increased speed, and incredibly tiny area requirements. The two most important building blocks of QCA nano computing are the multiplexer and demultiplexer. The performance of new 2:1 multiplexer and 1:2 demultiplexer QCA layouts was investigated in this study. For a better performance study, two methodologies were used to measure energy loss, and alternative cost functions were explored. Total energy losses of 14.30 meV and 7.37 meV for the proposed multiplexer and demultiplexer, respectively, were detected using the software QDADesigner-E (QDE) in the Coherence vector simulation mode applying the Runge Kutta approximation technique. According to QCAPro, at the tunneling level 0.5EK and temperature 2K, the total energy loss of the multiplexer and the demultiplexer is 35.60 meV and 37.19 meV, respectively. Cost functions for both experimental items were also calculated in three different methods.

Design and Analysis of Fault-Tolerant 1:2 Demultiplexer Using Quantum-Dot Cellular Automata Nano-Technology

Quantum-dot Cellular Automata (QCA) is an innovative paradigm bringing hopeful applications in the perceptually novel computing layout in quantum electronics. The circuits manufactured by QCA technology can provide a notable decrease in size, rapid-switching velocity, and ultra-low power utilization. The demultiplexer is a beneficial component to optimize the whole process in any logical design, and therefore is very important in QCA. Moreover, fault-tolerant circuits can improve the reliability of digital circuits by redundancy. Hence, the present investigation illustrates a novel QCA-based fault-tolerant 1:2 demultiplexer construct that employs a two-input AND gate and inverter. The functionality of the suggested layout was executed and evaluated with the utilization of the QCADesigner 2.0.3 simulator. This paper utilizes cell redundancy on the wire, inverter, and AND gates for designing a fault-tolerant demultiplexer. Four components (i.e., missing cells, dislocation cells, extra cells, and misalignment) were analyzed by the QCADesigner simulator. The simulation results demonstrated that our proposed QCA-based fault-tolerant 1:2 demultiplexer acted more efficiently than prior constructs regarding delay and fault tolerance. The proposed fault-tolerant 1:2 demultiplexer could attain high fault-tolerance when single missing cell or extra cell faults exist in the QCA layout.

Multi-Port Memory Design in Quantum Cellular Automata Using Logical Crossing

Memory and its data communication are very significant in the Processor design and its performance. In order to attain high performance computing machine, the memory access has to be equally faster. Here in this paper, Dual port memory with Set/Reset is designed using Majority Voter in Quantum-dot Cellular Automata (QCA). Dual port memory consists of basic functional blocks such as 2 to 4 decoder, Control Logic Block (CLB), Address Checker Block (ACB), Memory Cell (MC), Data Router block and Input / Output block. These functional units are constructed using the 3-input majority voters. QCA is one of the recent technologies for nano-metric design of digital components. The functional simulation of Dual Port Memory design is verified using QCA. A novel crossover method called Logical Crossing is utilized to improve the area of the proposed design. The logical crossing does the data transmission with the support of proper Clock zone assignment. The logical crossing based QCA layouts are optimized in terms of area and number of cell counts. It is observed that 29.81%, 18.27%, 8.32%, 11.57% and 3.69% are percentage of improvement in number of cells in Decoder, ACB, CLB, Data Router and Memory Cell respectively. Also, 25.71%, 16.83%, 8.62%, 4.74% and 3.73% of improvement in area for Decoder, ACB, CLB, Data Router and Memory Cell respectively. In addition to that the proposed Dual port memory using logical crossing attains 8.26% of area and 8.65 % of number of cells improvement. Moreover, the quantum circuits of the RAM are obtained and quantum cost, constant inputs, number of gates, garbage output and total cost are estimated as 285, 67, 57, 50 and 516 respectively.

Systematic cell placement in quantum‐dot cellular automata embedding underlying regular clocking circuit

Quantum-dot cellular automata (QCA) is gaining worldwide popularity due to its higher device concentration, lower power indulgence, and better switching speed. The information flows in QCA with the polarization state defined by the placement of electrons instead of current flow. The cell interaction principle under the influence of the clocking zone controls the cell placement during QCA circuit design. Most of the designs reported so far used random cell placement, which has no fabricating sense. Moreover, it is equally important for a cell placement algorithm to follow a realistic, regular underlying clocking scheme to maintain proper routing channels. In this regard, a systematic cell placement for the combinational logic circuit in QCA is proposed using the widely accepted underlying regular clocking scheme, universal, scalable and efficient (USE). The proposed method traverses all possible paths of a combinational logic circuit from output to input to build the desired circuit generating the automatic cell layout. A grid of clock zone of USE clock scheme is considered in the initial layout driving different paths of the circuit and finally evolves as the desired circuit. The generated automatic QCA layouts are competitive in occupied area, delay, and its cell count, which advocates the significance of such a scheme.

CFA: Toward the Realization of Conservative Full Adder in QCA with Enhanced Reliability

The significant physical challenges of Complementary Metal Oxide Semiconductor (CMOS) technology drives it on the brink of ultimate limit. With the surfacing of tremendous research findings, Quantum dot cellular automata (QCA) has emerged as a new technology in nanoscale era as a viable alternative to CMOS technology. Besides its wide acceptance, QCA-based nanoscale circuits are highly susceptible to huge fault/error rates. Thus, the fault tolerance and testability have become the utmost necessity for ensuring reliable QCA circuit. Toward this direction, conservative logic plays a vital role to achieve such reliability. In this paper, a Conservative Full Adder (CFA) is proposed with a simplified testable logic to detect the internal fault in the circuit. A simple majority–minority-based testing logic in the circuit is augmented for the detection of conservative (bit preserving) nature. Besides the testable feature, the full adder is chosen for its versatility in Arithmetic and Logic Unit (ALU) synthesis. Experimental result establishes the superiority of the proposed logic in terms of design capability as well as testability. Also, a comprehensive analysis of energy dissipation is performed to ensure the robustness of the proposed testable conservative adder. The QCA layout design and functional verification of the design are performed using the QCADesigner tool and Hardware Description Language for QCA (HDLQ) tool, respectively. The QCAPro simulator is used to evaluate the energy dissipation of the circuit.

BCD Adder Designs Based on Three-Input XOR and Majority Gates

Lots of emerging techniques can natively realize majority-of-three (MAJ) gates. Although enhanced gates such as exclusive-OR (XOR) gates can be implemented by several MAJ gates, there exists much efficient XOR design which directly derived by the physical attributes of emerging techniques. In this brief, we proposed multi-digit binary coded decimal (BCD) adder designs represented based on three-input exclusive-OR (XOR <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) and MAJ gates. BCD adder is widely used in financial, commercial, and industrial computing. We implemented the designs using quantum-dot cellular automata (QCA) technology. The proposed logic representations are validated using different types of binary adders as well as QCA design strategies. The introduction of XOR <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gates is conducive to achieve compact logic representations, which positively affect both the area and delay of QCA layouts. Compared with the existing best designs, the proposed 1-digit BCD adder has 50% less area and 10% less delay, and the 8-digit BCD adder has a 3.42× improvement of area-delay product.

Utilizing charge reconfigurations of quantum-dot cells in building blocks to design nanoelectronic adder circuits

In the quantum-dot cellular automata (QCA) nanotechnology, the cell-based building block can be designed by utilizing the charge reconfiguration of quantum-dot cells in order to achieve the desired function with optimal implementation. In this paper, new advanced nanostructures based on quantum-dot cells are introduced to three-input XOR gate and two-to-one multiplexer, which can be considered in addition to the conventional majority voter as basic building blocks used in implementing well-optimized QCA circuits. Consequently, these blocks are used in this paper to implement new single-layer QCA full-adders and four-bit adders as motivational applications. Moreover, an innovative design approach of full-adder is proposed to avoid the presence of inputs surrounded by QCA cells and to prevent the use of crossovers when building multi-bit adders. The proposed QCA layouts are simulated and evaluated as results indicate that proposed designs are superior to the previous designs in the literature.

Implementation of the new SCV method in quantum‐dot cellular automata

Quantum-dot cellular automata (QCA) is a novel nanodevice that implements logic circuits at the nanoscale. Information encryption is a key issue in nanocommunications. This article proposes a new method ‘select, cross, variation’ (SCV) for data encryption. This work also implements the QCA layout of this method for the first time. The QCA-based SCV circuit uses 71 cells. The circuit is composed of six majority gates and two inverters. The total area of the QCA circuit is 0.08 μm2. The area of all the Cells' is 0.025 m2, accounting for 31.19% of the total area. The circuit delay is 1 clock cycle. In addition, no cross wires are used in the circuit. Comparing the theoretical values with the simulation results of QCADesigner, the design accuracy of the circuit is verified. The circuit's computational capabilities under thermal randomness is estimated, thus establishing the stability of the proposed circuit. The estimation of energy dissipation proves that the proposed circuit consumes very low energy.

The design and implementation of a robust single-layer QCA ALU using a novel fault-tolerant three-input majority gate

Inverter and majority gates are considered as two important primitive gates for designing logical circuits in the quantum-dot cellular automata (QCA) technology. Up to now, many QCA layouts have been introduced for three-input majority gates, most of which are not robust against the QCA defects and so they are prone to faults. In this paper, we propose an efficient fault-tolerant 3-input majority gate with ten simple and rotated cells whose output signal strength is very high (± 9.93e−001). The fault tolerance of the proposed structure is investigated against cell omission, extra-cell deposition, and displacement defects. The results show that the proposed structure is 100% and 90% tolerant against single-cell omission and extra-cell deposition defects. Moreover, the error probability of the proposed gate under cell omission and extra-cell deposition defects is investigated through analytical modeling. Using the proposed fault-tolerant structure, two basic circuits including a fault-tolerant QCA full-adder and a fault-tolerant 2:1 QCA multiplexer are introduced. Finally, using the proposed circuits, a fault-tolerant one-bit arithmetic logic unit with four mathematical and logical operations is designed and implemented. To verify the proposed three-input majority gate, some physical proofs are provided. The results of simulations by QCADesigner 2.0.3 show that the proposed circuits work well. The power analysis of the proposed structure is performed using a QCAPro tool. The comparison results show that the proposed circuits are much better than the previous designs.

A High-Performance Design of Generalized Pipeline Cellular Array

In this letter, we proposed a high-performance quantum-dot cellular automata (QCA) design of generalized pipeline cellular array (GPCA). The GPCA can perform all the basic arithmetic operations using only one arithmetic cell. Due to its flexibility, the high-performance GPCA design is of high interest for large-scale QCA designs. We proposed both the arithmetic unit and control unit designs of GPCA using a hybrid logic network that represented by majority-of-three (MAJ), inverter (NOT), and three-input exclusive-OR (XOR 3 ). The introduction of XOR 3 operation can significantly reduce the number of gates, levels, and wire-crossings, which in turn results in less area and fewer clock cycles of QCA layout. Experiments show that we can achieve both area and latency improvements of n-bit (n = 3,4,5) GPCA designs compared with the-state-of-art.

An Optimized Counter Design using T Flip-Flop in Quantum-Dot Cellular Automata Technology

Conventional CMOS technology have lot of limitations and serious challenges threat this technology when scaled to a nano-level. Several alternative technologies have been proposed as solutions to overcome limitations and challenges encountered by CMOS. Quantum dot-cellular automata (QCA) is an emerging nanotechnology for the development of logic circuits such as combinational and sequential circuits.QCA seems to be best alternative to the conventional complementary metal-oxide semiconductor (CMOS) technology.QCA is a new computing paradigm in nanotechnology that can implement digital circuits with outstanding features such as ultralow power consumption, faster switching speed and extremely density structure . In this paper , a novel area efficient and optimized QCA layout design of sequential circuit T flip flop is proposed by which the QCA layout area has reduced by 57% , cell count improved by 56% in comparison with the earlier best designs. The use of proposed T flip flop in designing sequential circuits like synchronous 2 bit up counter,3 bit up counter and 4 bit up counter has reduced the QCA layout area by 65%,64% and 68% respectively where as QCA cell count are reduced by 53%, 62% and 59%.. The sequential circuits flip flop and counters are designed using three input XOR gate and are implemented by QCA layout. The paper also present the use of proposed T flip flop designed with 3 input XOR gate in designing not only synchronous binary up counters but also in synchronous binary down counter provides a significant reduction in the hardware and complexity than the existing methods. These circuits are simulated using computer aided design tool QCA Designer 2.0.3, which is a design and simulation tool for quantum dot cellular automata. The aim is to maximize the circuit density and focus on a QCA layout that uses minimal number of cells

Novel design of reversible priority encoder in quantum dot cellular automata based on Toffoli gate and Feynman gate

In accordance with Moore’s law, the size of complementary metal oxide semiconductor (CMOS)-based devices keep shrinking to augment the density on the chip. This scaling influences the execution of CMOS device due to several constraints like energy dissipation and synchronization of different components of the device. In non-reversible logic gates, power loss is the major concerned. Interest in reversible logic-based circuit design is increased as it offers reduced heat dissipation. Quantum dot cellular automata (QCA) is the possible implementation platform for reversible circuits. An encoder is an important component of memory, for address decoding and encoding. In this article, reversible logic-based architecture of 4 to 2 and 8 to 3 priority encoder is proposed and implemented on QCA platform. To design the encoder circuit, a new QCA layout of Feynman gate and Toffoli gate has been employed. The proposed layout of Feynman gate and Toffoli gate outshines the existing state-of-the-art designs. Quantum cost and circuit cost estimation of those encoder circuits are also performed. QCADesigner tool has been used to validate the performance of the proposed QCA reversible encoders.

An Architecture of 2-Dimensional 4-Dot 2-Electron QCA Full Adder and Subtractor with Energy Dissipation Study

Quantum-dot cellular automata (QCA) is the beginning of novel technology and is capable of an appropriate substitute for orthodox semiconductor transistor technology in the nanoscale extent. A competent adder and subtractor circuit can perform a substantial function in devising arithmetic circuits. The future age of digital techniques will exercise QCA as preferred nanotechnology. The QCA computational procedures will be simplified with an effective full adder and subtractor circuit. The deficiencies of variations and assembly still endure as a setback in QCA based outlines, and being capricious and inclined to error is the limitation of these circuits. In this study, a new full adder and subtractor design using unique 3-input XOR gate with cells redundancy is proposed. This designs can be utilized to form different expedient QCA layouts. The structures are formed in a single layer deprived of cross-wiring. Besides, this study is directed to the analysis of the functionality and energy depletion possessions of the outlined full adder and subtractor circuits. For the first time, QCADesigner-Energy (QD-E) version 2.0.3 tool is utilized to find the overall depleted energy. The attained effects with QCADesigner have verified that the outlined design has enhanced functioning in terms of intricacy, extent, and latency in contrast to the earlier designs. Moreover, the redundant form of full adder and subtractor has uncomplicated and robust arrangement competing typical styles.

Robust and efficient QCA cell-based nanostructures of elementary reversible logic gates

Increasing device density and reducing energy consumption are challenging issues in integrated nanoscale circuits. Reversible logic in quantum-dot cellular automata (QCA) nanotechnology is emerging as a promising candidate to overcome these issues and to introduce new computation paradigms with unique features like nanoscale feature size and ultra-low power dissipation. For the first time, QCA cell-based designs of reversible Feynman, Toffoli, Fredkin, and Peres gates are presented in this paper. These elementary gates are usually used in the synthesis of reversible circuits. The proposed layouts utilize electrostatic interactions between cells within QCA configurations to perform desired functions. All the robust designs are evaluated in terms of hardware complexity and power dissipation using QCADesigner and QCAPro simulation tools. The efficient QCA layouts of proposed gates have notable improvements as compared to the existing ones in terms of gate delay, cell count, area occupation, quantum cost, leakage energy, and switching energy. As a result, the proposed elementary gates via QCA cell level-based design are good candidates for building and developing high-level nanoelectronic reversible circuits.

A novel configurable flip flop design using inherent capabilities of quantum-dot cellular automata

One of the most attractive fields in quantum-dot cellular automata (QCA) is the implementation of configurable structures. In this paper, a novel QCA structure of a configurable flip-flop (CFF) element is introduced. In a bottom-up design approach, this paper firstly proposes well-organized QCA layouts for a positive/negative clock signal generator, a level/edge pulse converter, and a bit transport/toggle storage block. In the next step, these blocks are connected in a cascade construction to form a robust and efficient flip-flop element with a comprehensive configurable capability. The simulation results demonstrate the accuracy of proposed QCA-based structures. Design capability and flexibility of the proposed CFF element are further evaluated through the synthesis of high-level circuits including registers and counters. Consequently, this new element is the best building block to be used in the next generation of configurable systems such as QCA-based FPGAs.