Quantum Circuit Design Research Articles

Quantum circuit design of approximate median filtering with noise tolerance threshold

Quantum median filtering is an important step for many quantum signal processing algorithms. Current quantum median filtering designs show limitations in either computational complexity or incomplete noise detection. We propose a design of quantum median filtering, which uses approximate median filtering with noise tolerance threshold to remove salt-and-pepper noise. Instead of calculating the median, we search an approximate median by sorting four times, which reduces the computational complexity from $$O\left( {21{q^2} + 63q} \right) $$ to $$O\left( {12{q^2} + 36q} \right) $$. Here, q is the qubit used to represent the gray value. Furthermore, we adopt a two-level threshold to detect the noise points as much as possible. Finally, we design a complete quantum circuit to implement the approximate median filtering. The computational complexity of our proposed circuit is $$O\left( {10{n^2} + 14{q^2}} \right) $$ for a NEQR quantum image with a size of $${2^n} \times {2^n}$$. The complexity analysis shows that our proposed method significantly speeds up the filtering process compared with the classical filtering methods and the existing quantum filtering methods. In addition, the simulation results prove the proposed approximate median filtering is feasible.

Quantum image processing algorithm using edge extraction based on Kirsch operator.

In this work, a quantum image processing algorithm is developed using the edge extraction method together with the Kirsch operator. In our approach, novel enhanced quantum representation (NEQR) is employed as the image representation model for processing quantum image, which generates results of edge extraction using the Kirsch operator. The proposed algorithm can perform real-time image processing with high accuracy. We carry out the design, analyses, and simulations of quantum circuits based on our approach, which shows that the image processing speed and acuracy are much better than the classical edge extraction algorithms.

Mathematical formulation of quantum circuit design problems in networks of quantum computers

In quantum circuit design, the question arises how to distribute qubits, used in algorithms, over the various quantum computers, and how to order them within a quantum computer. In order to evaluate these problems, we define the global and local reordering problems for distributed quantum computing. We formalise the mathematical problems and model them as integer linear programming problems, to minimise the number of SWAP gates or the number of interactions between different quantum computers. For global reordering, we analyse the problem for various geometries of networks: completely connected networks, general networks, linear arrays and grid-structured networks. For local reordering, in networks of quantum computers, we also define the mathematical optimisation problem.

A quantum algorithm for automata encoding

Encoding of finite automata or state machines is critical to modern digital logic design methods for sequential circuits. Encoding is the process of assigning to every state, input value, and output value of a state machine a binary string, which is used to represent that state, input value, or output value in digital logic. Usually, one wishes to choose an encoding that, when the state machine is implemented as a digital logic circuit, will optimize some aspect of that circuit. For instance, one might wish to encode in such a way as to minimize power dissipation or silicon area. For most such optimization objectives, no method to find the exact solution, other than a straightforward exhaustive search, is known. Recent progress towards producing a quantum computer of large enough scale to surpass modern supercomputers has made it increasingly relevant to consider how quantum computers may be used to solve problems of practical interest. A quantum computer using Grover?s well-known search algorithm can perform exhaustive searches that would be impractical on a classical computer, due to the speedup provided by Grover?s algorithm. Therefore, we propose to use Grover?s algorithm to find optimal encodings for finite state machines via exhaustive search. We demonstrate the design of quantum circuits that allow Grover?s algorithm to be used for this purpose. The quantum circuit design methods that we introduce are potentially applicable to other problems as well.

Design of Quantum Computing Circuits

Quantum computing is an emerging method of computation that promises to accomplish computational tasks and algorithms that are too difficult to perform on existing computing paradigms. Some of the promising applications of quantum computing includes number theory, encryption, search, and scientific computation. Circuits must be designed to apply quantum machines to these applications. This work introduces quantum circuit design. We provide a brief introduction to quantum computing, and then, we illustrate gates used in quantum circuit design. We conclude by introducing quantum circuits for arithmetic operations.

Quantum circuit design for several morphological image processing methods

Morphological image processing is a relatively mature image processing method in classical image processing. However, in quantum image processing, the related results are still quite scarce. In this paper, we first design the quantum circuits of the two basic operations of dilation and erosion for binary images and grayscale images. On this basis, for binary image, the quantum circuits of three morphological algorithms (noise removal, boundary extraction and skeleton extraction) are designed in detail. For grayscale image, the quantum circuits of three morphological algorithms (i.e., edge detection, image enhancement and texture segmentation) are also designed. In the design of these circuits, the parallelism of quantum computation is considered. The analysis of the circuits complexity shows that all the six morphological algorithms can speed up their classic counterparts.

Parametric Approach for Routing Power Nets and Passive Transmission Lines as Part of Digital Cells

In design and layout of rapid single flux quantum circuits, multiple independent biases are often desired to provide flexibility in timings of critical paths. In absence of automated power routing, power nets are often included as part of the layout cells. Multiple variants of each cell need to be manually created to support different biasing configurations. The parametric approach for routing power nets provides the flexibility to dynamically change biasing configurations, based on the same parametric cell. Multiple cells in a circuit block can be configured to be connected to a single power net or can be biased using several independent power nets. With the goal of minimizing the cell size, it is often difficult to maintain rotational symmetry for the power and passive transmission line (PTL) tracks. The parametric approach also enables rotating the cell while avoiding misalignment of the tracks. In addition, our implementation can dynamically add moat bridges to connect ground planes isolated by moats. This is especially useful to bridge very long moats that span two or more adjacent cells. Furthermore, this approach of dedicated tracks for power and PTL routing is also more amenable to design automation.

Quantum circuit design for objective function maximization in gate-model quantum computers

Gate-model quantum computers provide an experimentally implementable architecture for near-term quantum computations. To design a reduced quantum circuit that can simulate a high-complexity reference quantum circuit, an optimization should be taken on the number of input quantum states, on the unitary operations of the quantum circuit, and on the number of output measurement rounds. Besides the optimization of the physical layout of the hardware layer, the quantum computer should also solve difficult computational problems very efficiently. To yield a desired output system, a particular objective function associated with the computational problem fed into the quantum computer should be maximized. The reduced gate structure should be able to produce the maximized value of the objective function. These parallel requirements must be satisfied simultaneously, which makes the optimization difficult. Here, we demonstrate a method for designing quantum circuits for gate-model quantum computers and define the Quantum Triple Annealing Minimization (QTAM) algorithm. The aim of QTAM is to determine an optimal reduced topology for the quantum circuits in the hardware layer at the maximization of the objective function of an arbitrary computational problem.

Quantum Circuit Designs of Integer Division Optimizing T-count and T-depth

Quantum circuits for mathematical functions such as division are necessary to use quantum computers for scientific computing. Quantum circuits based on Clifford+T gates can easily be made fault-tolerant but the T gate is very costly to implement. The small number of qubits available in existing quantum computers adds another constraint on quantum circuits. As a result, reducing T-count and qubit cost have become important optimization goals. The design of quantum circuits for integer division has caught the attention of researchers and designs have been proposed in the literature. However, these designs suffer from excessive T gate and qubit costs. Many of these designs also produce significant garbage output resulting in additional qubit and T gate costs to eliminate these outputs. In this work, we propose two quantum integer division circuits. The first proposed quantum integer division circuit is based on the restoring division algorithm and the second proposed design implements the non-restoring division algorithm. Both proposed designs are optimized in terms of T-count, T-depth and qubits. Both proposed quantum circuit designs are based on (i) a quantum subtractor, (ii) a quantum adder-subtractor circuit, and (iii) a novel quantum conditional addition circuit. Our proposed restoring division circuit achieves average T-count savings from 79.03 to 91.69 percent compared to the existing works. Our proposed non-restoring division circuit achieves average T-count savings from 49.22 to 90.03 percent compared to the existing works. Further, both our proposed designs have linear T-depth. We also illustrate the application of the proposed quantum division circuits in quantum image processing with a case study of quantum bilinear interpolation.

Quantum Circuit Design of a T-count Optimized Integer Multiplier

Quantum circuits of many qubits are extremely difficult to realize; thus, the number of qubits is an important metric in a quantum circuit design. Further, scalable and reliable quantum circuits are based on fault tolerant implementations of quantum gates such as Clifford+T gates. An efficient quantum circuit saves quantum hardware resources by reducing the number of T gates without substantially increasing the number of qubits. This work presents a T-count optimized quantum circuit for integer multiplication with only $4 \cdot n + 1$4·n+1 qubits and no garbage outputs. The proposed quantum multiplier design reduces the T-count by using a novel quantum conditional adder circuit. Also, where one operand to the conditional adder is zero, the conditional adder is replaced with a Toffoli gate array to further save T gates. Average T-count savings of $46.12$46.12, $47.55$47.55, $62.71$62.71 and 26.30 percent are achieved compared to the recent works by Kotiyal et al., Babu, Lin et al., and Jayashree et al., respectively.

Shaded tangles for the design and verification of quantum circuits.

We give a scheme for interpreting shaded tangles as quantum circuits, with the property that if two shaded tangles are ambient isotopic, their corresponding computational effects are identical. We analyse 11 known quantum procedures in this way—including entanglement manipulation, error correction and teleportation—and in each case present a fully topological formal verification, yielding generalized procedures in some cases. We also use our methods to identify two new procedures, for topological state transfer and quantum error correction. Our formalism yields in some cases significant new insight into how the procedures work, including a description of quantum entanglement arising from topological entanglement of strands, and a description of quantum error correction where errors are ‘trapped by bubbles’ and removed from the shaded tangle.

Realization of Quantum SWAP Gate Using Photonic Integrated Passive and Electro-optically Active Components

ABSTRACTWe report on the theoretical design and simulation of a photonic quantum circuit that operates as a single-photon, two-qubit swap gate. In this approach, the circuit is implemented in Titanium indiffused LiNbO3 channel waveguides, and polarization and spatial encoding are utilized to realize the qubits. A set of basic components comprising a dual periodically poled waveguide for two simultaneous Type-0 and Type-I non-linear interactions, as well as the passive routing and active electro-optically controllable devices, are the main building blocks in this circuit. Simulations are carried out by making use of the numerical beam propagation method incorporated within RSoft program package.

Faster manipulation of large quantum circuits using wire label reference diagrams

Large scale quantum computing is highly anticipated, and quantum circuit design automation needs to keep up with the transition from small scale to large scale problems. Methods to support fast quantum circuit manipulations (e.g. gate replacement, wire reordering, etc.) or specific circuit analysis operations have not been considered important and have been often implemented in a naive manner thus far. For example, quantum circuits are usually represented in term of one-dimensional gate lists or as directed acyclic graphs. Although implementations for quantum circuit manipulations are often only of polynomial complexity, the sheer number of possibilities to consider with increasing scales of quantum computations make these representations highly inefficient – constituting a serious bottleneck. At the same time, quantum circuits have structural characteristics, which allow for more specific and faster approaches. This work utilises these characteristics by introducing a dedicated representation for large quantum circuits, namely wire label reference diagrams. We apply the representation to a set of very common circuit transformations, and develop corresponding solutions which achieve orders of magnitude performance improvements for circuits which include up to 80 000 qubits and 200 000 gates. The implementation of the proposed method is available online.

Rashba control to minimize circuit cost of quantum Fourier algorithm in ballistic nanowires

The presented work provides a new prospective of quantum computer hardware development through ballistic nanowires with Rashba effect. We address Rashba effect as a possible mechanism to realize novel qubit gates in nanowires. We apply our results to the design of a new quantum circuit for Fourier algorithm, which shows an improved quantum cost in terms of the number of gates. The current system can be successfully implemented to increase the production of quantum computer experimentally thanks to the absence of impurities. The introduced circuit will enhance the scope of experimental and theoretical research for the realization of other quantum algorithms, such as phase estimation and Shor's algorithms.

Quantum Circuit Realization of Morphological Gradient for Quantum Grayscale Image

In this paper, based on the principle of classical morphology operations, the flat grayscale dilation and erosion operations are proposed for NEQR quantum image model. Furthermore, through combining these two morphology operations, we further realize the morphological gradient operation. As the basis of designing of grayscale morphology operations, a series of quantum circuit designs arepresented, which includes special add one operation UA1(n) and special subtract one operation US1(n) both for an n-length qubits sequence, quantum unitary operation UC, parallel subtractor (PS) module, quantum comparator output the large QCOL and quantum comparator output the small QCOS modules. When designsthe concrete quantum circuit, a sequence of UA1(n) and US1(n) modules are used to obtain the quantum image sets based on the shape of specific structuring element. Then, the searching for maximaor minima in a certain space is involved, which can be solved by cascading a series of QCOL and QCOS modules in certain order. Finally, the PS module can be used to calculate the difference of the maxima and minima for producing the morphological gradient. The circuit’s complexity analysis illustrate that our scheme is very lower to the classical morphology operations.

A template-based technique for efficient Clifford+T-based quantum circuit implementation

The near-future possibility of Quantum supremacy, which aspires to establish a set of algorithms running efficiently on a Quantum computer – have significantly fuelled the interest in design and automation of Quantum circuits. Multiple technologies such as Ion-Trap, Nuclear Magnetic Resonance (NMR), have made great progress in recent years towards a practical Quantum circuit implementation. For all these technologies, in order to suppress the inherent computation noise, fault-tolerance is a desirable feature. Fault tolerance is achieved by Quantum error correction codes, such as surface code. Due to the efficient realization of surface codes using Clifford + T gate library of Quantum logic gates, it is now becoming de facto gate library for Quantum circuit implementation. In this paper, we improve two key performance metrics, T − depth and T − count, for Quantum circuit realization using Clifford + T gates. In contrast with the previous approaches, we have incorporated two techniques - 1) restructuring of the gate positions in the designs to make it amenable towards a lower T − depth 2) using Binary Decision Diagrams (BDD) as an intermediate representation for achieving scalability. To validate our proposed optimizations, we have tested a wide spectrum of benchmarks, registering an average improvement of 74% and 21% on T − depth and T − count in compared works.

Loss Mechanisms and Quasiparticle Dynamics in Superconducting Microwave Resonators Made of Thin-Film Granular Aluminum.

Superconducting high kinetic inductance elements constitute a valuable resource for quantum circuit design and millimeter-wave detection. Granular aluminum (grAl) in the superconducting regime is a particularly interesting material since it has already shown a kinetic inductance in the range of nH/□ and its deposition is compatible with conventional Al/AlOx/Al Josephson junction fabrication. We characterize microwave resonators fabricated from grAl with a room temperature resistivity of 4×10^{3} μΩ cm, which is a factor of 3 below the superconductor to insulator transition, showing a kinetic inductance fraction close to unity. The measured internal quality factors are on the order of Q_{i}=10^{5} in the single photon regime, and we demonstrate that nonequilibrium quasiparticles (QPs) constitute the dominant loss mechanism. Weextract QP relaxation times in the range of 1s and we observe QP bursts every ∼20 s. The current level of coherence of grAl resonators makes them attractive for integration in quantum devices, while it also evidences the need to reduce the density of nonequilibrium QPs.

Is error detection helpful on IBM 5Q chips?

This paper reports on experiments realized on several IBM~5Q chips which show evidence for the advantage of using error detection and fault-tolerant design of quantum circuits. We show an average improvement of the task of sampling from states that can be fault-tolerantly prepared in the [4,2,2] code, when using a fault-tolerant technique well suited to the layout of the chip. By showing that fault-tolerant quantum computation is already within our reach, the author hopes to encourage this approach.

T-count and Qubit Optimized Quantum Circuit Design of the Non-Restoring Square Root Algorithm

Quantum circuits for basic mathematical functions such as the square root are required to implement scientific computing algorithms on quantum computers. Quantum circuits that are based on Clifford+T gates can easily be made fault tolerant, but the T gate is very costly to implement. As a result, reducing T-count has become an important optimization goal. Further, quantum circuits with many qubits are difficult to realize, making designs that save qubits and produce no garbage outputs desirable. In this work, we present a T-count optimized quantum square root circuit with only 2 ṡ n + 1 qubits and no garbage output. To make a fair comparison against existing work, the Bennett’s garbage removal scheme is used to remove garbage output from existing works. We determined that our proposed design achieves an average T-count savings of 43.44%, 98.95%, 41.06%, and 20.28% as well as qubit savings of 85.46%, 95.16%, 90.59%, and 86.77% compared to existing works.

Design and implementation of a multivalued quantum circuit for threshold based color image segmentation

Design and implementation of a multivalued quantum circuit for threshold based color image segmentation