Quality Factor Of Inductor Research Articles

Design of Low Noise Amplifier Based on Tuneable Active Inductor and Capacitor for Bluetooth Applications

Active components such as active inductors and active capacitors have been used to replace their passive counterparts, especially in radio frequency modules. Besides saving colossal silicon area, active inductors are power saviors, tuneable, and provide large inductance ranges. This paper presents the evaluation and performance of a low noise amplifier (LNA) implemented using only active components. The active inductor has a high inductance tunability range from 848 nH to 1660 nH, resulting in a frequency range from 1.85 GHz to 3.02 GHz. The active inductor's quality factor is 11, with a maximum power dissipation of 208.1 µW from a 0.5 V DC power supply. The LNA provides a voltage gain of 8.76 dB with a noise figure of 8.21 dB while consuming 779.16 µW from a 0.85 V supply. The achieved frequency range is commonly used for various wireless communication applications, including Wi-Fi and Bluetooth.

Design and Characterisation of a Novel Z-Shaped Inductor-Based Wireless Implantable Sensor for Surveillance of Abdominal Aortic Aneurysm Post-Endovascular Repair.

An abdominal aortic aneurysm (AAA) is a dilation of the aorta over its normal diameter (> 3 cm). The minimally invasive treatment adopted uses a stent graft to be deployed into the aneurysm by a catheter to flow blood through it. However, this approach demands frequent monitoring using imaging modalities that involve radiation and contrast agents. Moreover, the multiple follow-ups are expensive, time-consuming, and resource-demanding for healthcare systems. This study proposes a novel wireless implantable medical sensor (WIMS) to measure the aneurysm growth after the endovascular repair. The proposed sensor is composed of a Z-shaped inductor, similar to a stent ring. The proposed design of the sensor is explored by investigating the inductance, resistance, and quality factor of different possible geometries related to a Z-shaped configuration, such as the height and number of struts. The study is conducted through a combination of numerical simulations and experimental tests, with the assessment being carried out at a frequency of 13.56 MHz. The results show that a higher number of struts result in higher values of inductance and resistance. On the other hand, the increase in the number of struts decreases the quality factor of the Z-shaped inductor due to the presence of high resistance from the inductor. Moreover, it is observed that the influence of the number of struts present in the Z-shaped inductor tends to decrease for larger radii. The numerical and experimental evaluation concludes the ability of the proposed sensor to measure the size of the aneurysm.

Tunable RF MEMS Inductors for Two-Frequency Bands

This paper presents the design and simulation of two-variable MEMS inductors for high-frequency applications. In two cases, the inductors' cores are enclosed between two tunable metal plates. The medium permeability changes in response to iron plate movement, ensuring a high-tuning range above 250%. The first inductor is designed for the 10 GHz range, and the inductance value is comprised of Lmin = 3.37 nH and increases to Lmax = 11.8 nH. Similar inductance values are obtained for the second inductor, but it is designed to work at 20 GHz. Furthermore, the maximum value of the quality factor of the second inductor is slightly higher than the first one and reaches Qmax = 17.5.

Technical Reviews of Power Loss Optimization in High-Frequency PSiPs—In Relation to Power Switches and Power Inductors

Power losses of switches and inductors are consistent challenges that hinder the development of high-frequency power supply in package (PSiP). This paper investigates the roadmap for power loss optimizations of switches and inductors in high-frequency PSiPs. Firstly, a size and parallel quantity design method to reduce power loss in an integrated Si LDMOSFET is provided with comprehensive consideration of switching frequency and power levels. Secondly, quality factors of different air-core inductors are analyzed with consideration of geometric parameters and skin effect, which provides the winding structure optimization to reduce power losses. The power losses of the integrated Si LDMOSFET and air-core inductors are both reduced to less than 10% of the output power at 1~100 MHz switching frequency and 0.1~10 W power level. Finally, based on the above optimizations, power losses of switches and inductors are calculated with switching frequency and power level. Combining the calculated results, this paper predicts the efficiency boundaries of PSiPs. Upon efficiency normalization with consideration of input and output voltage levels, all the predictions are consistent with the published literature. The efficiency predication error is 1~15% at 1~100 MHz switching frequency and 0.1~10 W power level. The above power loss optimizations improve the efficiency, which provides potential roadmaps for achieving high-frequency PSiPs.

A 25% Tuning Range 7.5–9.4 GHz Oscillator With 194 FoM T and 400 kHz 1/f₃ Corner in 40nm CMOS Technology

An 8-GHz VCO with class-F23 operation was realized in a 40 nm CMOS technology without ultra-thick metals. The class-F23 operation was enabled in a transformer-based LC tank to allow multiple impedance peaks in the common mode (CM) and the differential mode (DM) excitation. With the additional resonance at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2^{nd}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3^{rd}$ </tex-math></inline-formula> harmonic frequency, the circuit noise to phase-noise conversion and 1/f noise up-conversion are reduced significantly. In a 40 nm CMOS technology without ultra-thick metal, a patterned shielding structure was proposed to improve the inductor quality factor. A combined varactor and capacitor array is proposed to provide accurate matching for a desired resonance frequency ratio, reducing AM-FM conversion and it achieves a broad tuning range. With the proposed transformer-based LC bank and class-F23 operation, the oscillator achieves a phase noise of −150.8 dBc/Hz at 10 MHz offset from a 1.85 GHz carrier after an on-chip /4 divider, and the measured 1/f3 flicker noise corner is around 400 kHz. The oscillator core covers a 7.5–9.4 GHz frequency range for a 25% tuning range.

Effect of the Insulating Layer on the Properties of SMC Inductors

In inductor applications, different soft magnetic materials are used depending on the frequency range. Owing to powder metallurgy technology and to the increase in the implementation of innovative multifunctional materials, it is possible to find an alternative to the traditional magnetic materials of the inductance application sector. This study concerns a deep analysis related to soft magnetic composite materials. The insulating layer’s effect is investigated to explore the applicability of such materials to the inductor sector. Four coatings systems are selected and two types of samples are prepared in the shape of a toroid and a rod, which are tested in different operating conditions. The rod inductors are also compared with a traditional one, based on soft ferrite materials. This work aims to integrate data coming from different measuring devices: the useful small-signal measurements of an RLC meter are completed by large-cycle data measured through a hysteresigraph. Different parameters are considered for the investigation: magnetic permeability (maximum and initial), iron losses at different induction peak values, and inductor quality factor are the most important. The obtained results prove that each analysis type is not fully reliable without the other in determining the coatings’ effects on the SMC inductors’ performance. In the end, it is demonstrated that SMC inductances can be successfully applied in a particular frequency range.

A Low-Cost Novel Method to Fabricate Integrated Magnetic Core Inductor Embedded in Organic Substrate

The strong demand for 3-D packaging technology has accelerated the miniaturization of passive devices, and inductors are facing challenges because the inductance value will be sacrificed when the size is shrinking. Adding a magnetic core is one of the solutions due to its enhancement of inductance density but it will also add complexity to the fabrication process. However, previous research shows that the performance enhancement brought by the magnetic core could be shadowed by the process complexity. A novel method to fabricate the magnetic core inductors on flexible substrates is proposed in this work. The inductor has a stacking structure of three layers: the Cu trace layer, and the two layers of magnetic core (under and above the Cu). The Cu trace is patterned by the wet etch process on the flexible PCB, a polyimide layer is then coated and planarized on the Cu surface as insulation, and the upper layer magnetic core is directly sputtered on the Cu trace layer. For the lower magnetic core layer, a polyimide layer on the carrier wafer is prepared as the substrate and it is also patterned by the liftoff process. Then, the finished layers are aligned and bonded with a flip-chip bonder with high precision and efficiency. Before the whole fabrication process, the device patterns are designed and optimized by the finite-element analysis software. Finally, the finished devices are measured with the radio-frequency probe station. The result shows that the inductance density and the quality factor of the magnetic core inductor could be 3.61 nH/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 6.22, respectively, with the device size being only 0.95 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Compared with the air core inductor (ACI) with the same Cu trace pattern, the magnetic core inductor elevates the inductance by 10% and still keeps the same low profile, of which the thickness of the whole device is within 100 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> . These parameters are measured and extracted at 100 MHz and this is the potentially used frequency for the power delivery applications such as the in-chip integrated voltage regulators.

High-Q Resonator–Inductor Using LiNbO₃ Plate for Frequency Tuning in 1–5 GHz

In this article, a new high quality factor ( Q ) inductor with piezoacoustic plate acoustic wave (PAW) resonators is presented. As indicated by the investigation of the acoustic wave propagation characteristics and transducer materials, the coupling coefficient ( k2 ) of the shear-horizontal plate (SH0) mode that propagates in the LiNbO3 plate increases to 55.7%, which leads to a wide inductive bandwidth of 29%. The longitudinal and transversal spurious modes are inhibited through novel edge reflector design and transducer engineering. The peak inductor quality factor ( [Formula: see text]) of the acoustic resonator-inductor is obtained as 347, and a large range of inductance values are achieved to be up to 49 nH by regulating the interdigital transducer (IDT) number of fingers (NF). It is noteworthy that a larger inductance is realized in a more miniaturized device. Furthermore, the wavelength-scaling-induced physics is investigated for frequency tuning in 1-5 GHz, which reveals the multifrequency ability on a single chip of the SH0 acoustic resonator-inductor.

Evolution Trends and Paradigms of Low Noise Frequency Synthesis and Signal Conversion Using Silicon Technologies

Silicon technologies for HF applications have been proven for more than two decades, and technologies have greatly evolved. Whether CMOS or BiCMOS technologies, the unique combination of radio frequency, baseband, and digital functions allow a very high level of integration. While it is possible to achieve fully integrated transceivers, the major advantages of these silicon technologies lie mainly in their unparalleled performance in the field of frequency synthesis and frequency conversion. We propose in this paper a review of the major results obtained on these RF components since the beginning of the 2000s, also considering the impact of the technology node. The back-end of line (BEOL) process on which depends the quality of microwave monolithic integrated circuits (MMICs) is briefly presented in the introductory part. If circuit performances are tightly bound to the active devices (i.e., the heterojunction bipolar transistor SiGe HBT or CMOS transistor), passive elements (i.e., quality factor of inductors and varactors, losses of transmission, or interconnection lines) as well as the definition of the substrate also play a major role. The core of the article is oriented toward the noise of synthesized signals and frequency conversion. Frequency synthesis is presented through the analog design of a voltage-controlled oscillator (VCO) or through the direct digital frequency synthesis (DDFS), for which respective figures of merit are presented and discussed in a second section. The spectral purity of the oscillators being decisive in the definition of the throughput of a link is approached through the comparison of different figures of merit (FoM) for a set of circuits achievements over the selected period. If the realization of free oscillators is closely bound to the phase-locked loop (PLL)-type control loop for VCOs, the DDFS solution provides more direct and more flexible alternative at first sight. Therefore, these two solutions are analyzed collectively. Finally, the oscillator integrated in the transmitter or receiver supplies the needed LO (local oscillator) power to the frequency mixer in the frequency conversion module: henceforth, the third part of this study focuses on high-frequency mixer realizations. We thus consider this LO power in some advanced figure of merit mentioned in the second section. The design trade-off of the mixer is presented in an approach combining LO (conversion gain, channel isolation, and phase noise) and RF (HF noise figure and channel isolation) constraints. The final section provides a summary of the results and trends mentioned in the paper.

Analysis and design procedure of a mm-Wave Class-E power amplifier

This paper presents a Class-E Power Amplifier (PA) design procedure for operation at mm-Wave frequencies, which accounts for the loss of passive components, ON-resistance (Ron) of the transistor, and its breakdown voltage (VBr). The quality factor of inductors is modeled with equivalent resistors and integrated into time-domain equations for the first time. The proposed procedure is examined for the design of a 24 ​GHz Class-E PA in 130 ​nm CMOS technology and compared with former best-known design recipes in the same technology node. Besides, a simplified design technique is introduced based on Ron-Cout (Cout is the transistor output capacitance) curves of the transistor versus its width, obtained by Harmonic Balance (HB) simulation. By the proposed method, the Figure of Merit (FoM) of the designed PA, including a combination of the output power, efficiency, and maximum drain voltage, is improved significantly (52%) compared to the other procedure outcomes in the literature.

Approximate Equivalent Circuits to Understand Tradeoffs in Geometry of On-Chip Inductors

We develop an approximate frequency-independent equivalent circuit for integrated inductors on semiconducting substrates. All values of LCR in the equivalent circuit can be calculated directly from inductor geometry. The equivalent circuit captures: the skin effect, the proximity effect, the substrate capacitive loss, and the distributed capacitance. With careful definition of inductor quality factor, we are able to calculate the contribution of substrate capacitive loss and benefits of a substrate shield. Our model was put to test by successfully predicting the published quality factors of various inductors and proving that their geometries are close to optimum.

On-Chip Inductor in 0.18-μm CMOS for Low-Cost Fully Integrated Contactless Powered Sensors

Contactless sensors with CMOS on-chip antennas use only the top thick metal for the polarization antenna due to the low inductance contribution of the bottom (thin) CMOS metals adding only resistance to the antenna. In this letter, a two-layer inductor (thick top metal layer inductor in series with the bottom thin four-layer metal inductor) configuration was proposed for wireless polarization (by electromagnetic induction). The design proposed was simulated and fabricated in a 0.18- $\mu \text{m}$ CMOS process. The on-chip inductor powers a chip with a 1-mW load at a distance of 2 mm coupled with an external wireless power transmitter at 13.5 MHz with a 30-dBm output. The two-layer inductor configuration reduces the area required for the on-chip inductor by 38% and increases the on-chip inductor quality factor by 25% compared with a single-layer configuration, thus reducing the cost of fabricating fully integrated contactless sensors using only CMOS technologies.

A comparative study between Class-C and Class-B quadrature voltage-controlled power oscillator for multi-standard applications

In this paper a 0.35 ​mW Class-C/B series coupling quadrature voltage-controlled power oscillator (S-QVCO) based on the coupling between two identical LC VCOs is presented. The S-QVCO is designed using a 130 ​nm CMOS technology and it is suitable for multi-standard applications. High quality factor inductor is designed using the two top metal layers to enhance the phase noise performance of the VCO, also an improved switching varactor is used to achieve dual bands. The proposed QVCO achieves tuning range of 28.2% from 2.3 to 3.07 ​GHz, and low phase noise of −119.2 dBc at a 1-MHz offset frequency from 2.7 ​GHz carrier. By biasing the proposed QVCO in class-C, the DC current is reduced to 0.35 ​mA compared to 1.48 ​mA in class-B from 1 ​V supply voltage. The minimum achieved Figure-of-Merit (FOM) equals −192 dBc/Hz and the maximum given output power is 6.5 dBm. The phase error between quadrature output signals is maximum of 0.25° . The occupied area of the proposed QVCO equals0.34mm2, while the total chip area including RF pads is1mm2.

Laser-Based Fabrication of Microstructures on Nickel Thin Films and Its Applications in On-Chip Thin Film Inductors

This work reports on the fabrication of microbump structures on nickel (Ni) films by single-pulse, localized laser irradiation. Conditions for the reproducible formation of such microstructures have been identified in terms of laser-irradiation and film parameters after systematic studies involving a relevant parameter space. Ni films deposited by vacuum evaporation were found to be better suited for reproducible laser microstructuring because they lack the typical cracks and voids morphology of sputtered films. The continuous and smooth nature of the evaporated films facilitated a radially symmetric heat flow propagation upon laser irradiation, which then resulted in a complex combination of thermal expansion, deformation, and other processes leading to a high yield of microstructures. An improvement in the inductance and the quality factor of on-chip spiral inductors, incorporating such laser-microstructured ferromagnetic nickel thin films was observed, which demonstrates the potential of such a laser-based method for fabrication or fine tuning of various micro-/nano-electric/electronic sensor and other components and systems.

Design of a multilayer on-chip inductor by computational electromagnetic modelling

Abstract This paper presents a design of typical multilayer on-chip inductor to determine the layout parameters of the desired inductance value of electromagnetic modeling. The inductance and quality factor of multilayer on-chip spiral inductors are determined by its layout parameters and technological parameters. These layout parameters must be optimized to obtain the maximum quality factor at the desired frequency of operation. An electromagnetic model with fewer assumptions than empirical equations and higher efficiency than full-field solvers would be welcome. So would facile comparisons of different inductor structures. This paper describes recent works on the electromagnetic modeling of on-chip inductor structures applied to the comparison of inductor geometries, including the traditional spiral inductor and a novel multilayer inductor. The electromagnetic modeling of the investigative model is presented. The modeling and simulation are implemented using the method of moments. To simulate the proposed algorithm, the EM Simulator software is used.

Exploration of the 3-D Printing of Transformer Structures With Embedded Ferrite Cores

For inductor and transformer circuit components that operate at higher frequencies, the existence of parasitic capacitance due to the winding structure determines the device's self-resonance frequency. It is desirable to have precise design and manufacturing control over the winding structure to properly control this capacitance for reduced manufacturing variability, suggesting lithographic or computer numerical controlled (CNC) fabrication. Lithographic or CNC methods, however, reduce the possible number of winding turns due to the high aspect-ratio of vias, limiting the device inductance. A 3-D printing technology offers the opportunity to increase the aspect-ratio limitation by fabricating only a thin layer at one time. In this paper, the process of 3-D printing transformer structures was explored with multiple variations. A Voxel8 printer was mostly used, with the ability to print plastic as well as conductive silver paste. Commercial and custom MnZn ferrites were used as core materials, as well as printed magnetic polylactic acid (PLA) plastic using a dual-extruder MAKEiT Pro-M printer. Windings were fabricated by either silver paste deposition interleaved with plastic layers or post-fabrication silver ink injection. It was found that interleaved silver paste deposition produced very low resistance windings (high quality factor inductor) when compared with injected silver ink but had a high probability of shorting windings. Injected silver ink windings were found to have higher reliability only when the parts are properly printed liquid tight. Inductances were in agreement with theoretical predictions for most fabricated devices, and resistances were much higher for injected silver ink windings than interleaved printed windings. The best broadband transformer performance, which is an optimal low winding resistance and high mutual inductance, was found for a 36 mm outer diameter, 23 mm inner diameter, and 10 mm-thick MnZn ferrite core with an eight-turn printed winding.

On the Design of &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$n$ &lt;/tex-math&gt; &lt;/inline-formula&gt;th-Order Polyphase All-Pass Filters

A structure for $n$ th-order polyphase all-pass filters (PAFs) is proposed that improves the tradeoff between output phase accuracy and filter loss. The filter also has a well-defined input impedance, which is independent of the phase accuracy and can generate the exact desired phase at $n$ distinct frequencies. The proposed structure along with its design approach is analyzed. The design procedure to design a second, third, and fourth-order PAFs is presented. It is shown that by increasing the order of the PAF structure, one can either improve the phase accuracy of the structure over the same bandwidth of interest or achieve the same phase accuracy over a wider bandwidth. Practical design considerations, including the effect of the parasitic capacitances, component tolerance, and inductor quality factors on the output amplitude imbalance and input impedance, are analyzed and discussed. As a proof-of-concept, experimental results are presented to show that the fourth-order structure is able to generate quadrature signals at four distinct frequencies.

Photosensitive Glass-Ceramics for Heterogeneous Integration

The push for heterogeneous integration requires very unique material properties with respect to processing, material constants, and integration capabilities with other materials (such as copper, II...

Design and Implementation of Reference-Free Drift-Cancelling CMOS Magnetic Sensors for Biosensing Applications

Magnetic imagers, which utilize magnetic nanoparticles as labels to realize biodetection assays, hold significant promise for deployment at the point-of-use. Resonance-shift-based sensors can be realized in standard CMOS processes without post-process modifications and offer great sensitivity at low price tags. Unfortunately, CMOS resonant-shift magnetic sensors suffer significant degradation in SNR and long-term stability due to low on-chip inductor quality factors and significant noise introduced from active devices and thermal variations. This makes standard resonant-shift-based imagers undesirable for use in low-signal biodetection assays. Furthermore, and most importantly, the significant long-term drift due to slow-varying noise sources and temperature changes makes these sensors inadequate for bioexperiments which may take timescales on the order of hours to reach completion. In this paper, we propose a transformer-based approach which enables sub-parts-per-million (PPM) signal detection without the need for any thermal compensation. The approach is self-referencing, leading to significant savings in chip area by removing the need for replica reference cells. We analyze the performance of the transformer-based circuit compared to the original second-order system and demonstrate its superiority for rejecting system noise. A proof-of-concept design of a fully integrated $2 \times 2$ CMOS transformer-based magnetic sensor array is presented which achieves reference-free, sub-PPM detection of magnetic signals. The system can be powered and operated completely from a laptop USB interface and each sensing cell can consume less than 3 mW of DC power. Finally, we show the results of an initial DNA biodetection experiment which confirms the capability of the sensor to be used for realistic bioassays.

Load Mismatch Sensitivity of Class-E Power Amplifiers

Class-E RF power amplifiers (PAs) are very power efficient under nominal operating conditions. Due to incorporating two tuned tanks, the dependence on the load impedance is, however, relatively large, resulting in, e.g., load-dependent output power, power efficiency, peak voltages, and peak (and average) currents which can lead to reliability issues. This paper presents load–pull analyses for class-E RF PAs from a mathematical perspective, with analyses and discussions of the effects of the most common nonidealities of class-E PAs: the limited loaded quality factor ( $Q_{\mathrm {loaded}}$ ) of the series filter, switch ON-resistance, the limited quality factor of the dc-feed inductor, load mismatch-dependent switch conduction loss, and the limited negative voltage excursions (due to, e.g., the reverse conduction of the switch transistor for negative voltage excursions). The theoretical findings are backed up by extensive circuit simulations and load–pull measurements of a class-E PA implemented in 65-nm CMOS technology. The PA provides 18.1-dBm output power and 72% efficiency at 1.4 GHz under nominal operating condition employing an off-chip matching network.