Quadrupler Circuit Research Articles

Coupled‐inductor‐based high‐gain converter utilising magnetising inductance to achieve soft‐switching with low voltage stress on devices

This work proposes a soft-switched quadratic quadrupler boost converter with high voltage step up gain and low voltage stress on devices. With this converter topology, high voltage gain is achieved at low duty ratio operation of MOSFETs and few number of turns in coupled inductor. Operation at low duty ratio keeps boost converter gain in linear region and smaller number of turns in coupled inductor reduces the lossy part of the winding. Further, the magnetising inductance of coupled inductor is utilised to achieve zero voltage switching of MOSFETs to minimise the switching loss. In addition, secondary side diodes are operating under zero current switching conditions using resonance between leakage inductance and the capacitors of voltage quadrupler circuit. This greatly reduces the reverse recovery losses of the secondary side diodes. A detailed analysis of converter dynamics is discussed in one of the subsections to find out small-signal transfer functions with respect to variations in input voltage and duty ratio variation of MOSFETs. A 250 W prototype of the proposed converter is built and tested in laboratory with a maximum efficiency of ∼93% at 175 W output power.

A novel multiphase interleaved quadrupler circuit with reduced voltage stress and ripples for photovoltaic applications

A novel multiphase interleaved quadrupler circuit with reduced voltage stress and ripples for photovoltaic applications

A V‐band frequency quadrupler using subharmonic injection‐locked oscillator with push–push technique

ABSTRACTA V‐band frequency quadrupler with high output power characteristic has been implemented and fabricated using 0.15 µm GaAs pHEMT technology. This quadrupler circuit is achieved by a second‐order subharmonic injection‐locked oscillator and a push–push frequency doubler as the output buffer. The free‐running oscillation frequency of the core oscillator is around 35 GHz with a tuning range of 3.25 GHz covering from 33.25 to 36.5 GHz. Using push–push circuit to be a frequency doubler under a proper bias condition, an optimized second harmonic signal can be accomplished with high harmonic suppression. The frequency of output signal in the quadrupler can present a wide tuning range from 66.5 to 73 GHz, and the maximum output power is −1.25 dBm with total dc consumption of 56 mW. With injecting a second‐order subharmonic signal into the core oscillator, the circuit exhibits an injection locking with an output locking range of about 1.6 GHz from 69.2 to 70.8 GHz. The output phase noise for 70‐GHz signal can be improved better than −105 dBc/Hz at 1 MHz frequency offset when the injected signal power is higher than 0 dBm. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2473–2480, 2014

Low frequency properties of micro power generator using a gold electroplated coil and magnet

Abstract Micro power generating devices were fabricated by using a gold electroplated coil and a permanent magnet. The electrical power was generated when the magnet reciprocated on the fabricated electroplated coil. The output power was increased as a function of vibration frequency. A measurement system, which convert a rotational motion of a motor into a linear motion, was designed and fabricated. The purpose of this work is to develop the micro power generating devices which convert the ambient vibration or oscillating energy into useful electrical energy. With changing vibration frequency from 0.5 to 8 Hz, the generated power increased linearly. The generated voltage was 106 mV at 3 Hz and 198 mV at 6 Hz. After using the step up circuit, the measured voltage was 81 mV at 3 Hz and 235 mV at 6 Hz. From above the frequency of about 4.5 Hz, the gain obtained by using the quadrupler circuit becomes larger than the loss without using that circuit.

Compact and low power consuming frequency∕phase multiplier MMICs for wireless LAN at S-band and C-band

Active, monolithically integrated S-band (1.1-2.2 GHz) and C-band (2.2-4.4 GHz) frequency/phase doublers with ultra-compact circuit areas of less than 0.6 mm/sup 2/ and 0.5 mm/sup 2/, respectively, are presented using a commercial 0.6 /spl mu/m GaAs MESFET technology. These circuits were designed for low-power-consuming adaptive antenna receivers, operating in accordance with the high-performance radio local area network (HIPERLAN) and 802.11a standards. Cascading of the two doublers enables phase control range quadruplication of low cost phase shifters with 90/spl deg/ phase control range in the local oscillator (LO) path. Thus, a phase control range of 360/spl deg/ with low amplitude variations is reached in the radio frequency (RF) path, as required for adaptive antenna combining. Simulations performed using the modified MESFET large signal model show excellent agreement with measured results. At an ultra-low supply voltage of 0.9 V, a supply current of 5.8 mA and an input power of only -8 dBm, a conversion gain of 0.5 dB was measured for the quadrupler circuit. To the knowledge of the authors, the circuits present the best results for frequency multipliers in terms of power consumption and miniaturisation, reported to date.

Topological generation and analysis of voltage multiplier circuits

Voltage multipliers are used for transformerless conversion of an ac input voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">\upsilon_i(t)= E \sin \omega t</tex> into a dc output voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V_{out} = nE</tex> , where <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n \geq 2</tex> . This paper investigates the topological properties of voltage multiplier circuits and presents a unified approach for generating new voltage-multiplier circuit structures. In particular, an algorithm is presented for generating <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</tex> -fold voltage multipliers with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</tex> capacitors and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</tex> diodes. A theorem is presented for finding the dc capacitor voltages by inspection when no load current is drawn. For the case with load, explicit formulas for the output de voltage and the output resistance are given. Using the algorithm developed in this paper, three new voltage quadrupler circuits are generated and shown to have an output resistance only one-half of the conventional ladder quadrupler circuit.