Quadrature Voltage-controlled Oscillator Research Articles

An Ultra-Low Power QVCO Using Current-Coupling and Bulk-Injection Techniques

In this letter, a quadrature voltage-controlled oscillator (QVCO) using PMOS transistors to couple two VCO cores is presented. The power consumption is drastically reduced by using the bulk of the PMOS transistors to lower the transconductance of both differential pairs in the coupling network. The QVCO achieves a measured phase noise of ${-}116.02$ dBc/Hz at 1 MHz offset and a quadrature phase error of 0.48 $^{\circ}$ with a center frequency of 3.5 GHz. The proposed QVCO consumes 230 $\mu$ W from a 0.45 V supply voltage. The QVCO is implemented in a standard 0.13 $\mu$ m CMOS process with core area of 0.315 mm $^{2}$ .

An In-Phase-Coupled Class-C Quadrature VCO With Tunable Phase Error

This letter presents the design and analysis of a novel in-phase-coupled (IPC) Class-C Quadrature Voltage-Controlled Oscillator (QVCO) with tunable phase error. The IPC QVCO employs a novel coupling structure that generates in-phase coupling signal while consuming negligible power itself. IPC scheme enables the QVCO to achieve better phase noise and phase error compared to that of the conventional QVCO. The phase error of the proposed IPC QVCO is also tunable. The proposed IPC QVCO is fabricated using 0.18 μm CMOS technology and the measured output frequency range is from 2.5 to 2.97 GHz. At 2.623 GHz, with 3.6 mW power consumption, the phase noise at 1 MHz offset achieves -126.8 dBc/Hz while the phase error before phase error tuning is 0.5 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> . The measured phase error tuning range is ±17 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> .

Inside view

inside view

A 0.137 mm$^{{2}}$ 9 GHz Hybrid Class-B/C QVCO With Output Buffering in 65 nm CMOS

A compact realization of hybrid class-B/C quadrature voltage-controlled oscillator (QVCO) with output buffering is proposed. It employs a four-phase amplitude detector feedback loop to shift the operation mode from hybrid class-B/class-C to class-C after power up. The power-efficient class-C core allows quadrature-locking via passive capacitive coupling, whereas the auxiliary class-B core ensures a robust startup. For higher output drivability, PMOS-based source followers are stacked atop the QVCO for reusing its bias current and avoiding any AC-coupling networks. The buffered QVCO can directly drive up the 50- Ω port of testers, or to withstand a large capacitive load in on-chip signal distribution. The fabricated 9 GHz QVCO in 65 nm CMOS draws 10.5 mW and exhibits -99.37-dBc/Hz phase noise at 1 MHz offset. The active area is just 0.137 mm 2 by using two compact spiral inductors with patterned ground shields.

A 49-to-62 GHz Quadrature VCO With Bimodal Enhanced-Magnetic-Tuning Technique

A bimodal enhanced-magnetic-tuning technique is proposed to extend the frequency tuning range of millimeter-wave (mmW) quadrature VCOs (QVCOs). First, the conventional magnetic tuning is reviewed, and its limitations for the frequency tuning at mmW frequencies are high-lighted. To enlarge the variable range of the magnetic field, a new transformer-based topology called enhanced-magnetic-tuning (EMT) is proposed and analyzed. In addition, by switching the polarity of the phase shift of the coupling currents, both of the two intrinsic modes in a quadrature VCO are exploited to ideally double the frequency tuning range. With a generic model, the proposed bimodal enhanced-magnetic-tuning (B-EMT) is analyzed mathematically and compared with the conventional frequency tuning techniques. Implemented in a 65 nm CMOS process, the QVCO prototype with the proposed B-EMT technique and 1-bit digitally controlled varactor measures a tuning range of 24% from 48.8 to 62.3 GHz and phase noise of -89 to -96 dBc/Hz at 1 MHz offset while drawing 13 to 25 mA from a 1.2-V supply, corresponding to FoM from 173 to 176 dBc and FoMT from 181 to 184 dBc/Hz.

Differential rail‐to‐rail voltage‐controlled quadrature ring oscillator for low‐power implantable transceivers

A new low-power rail-to-rail voltage-controlled quadrature oscillator is presented. This oscillator was implemented to provide the frequency deviation of frequency-shift-keying (FSK) modulation in implantable radio-frequency (RF) transceivers. The quadrature oscillator circuit generates differential in-phase and quadrature-phase (I and Q) signals in a two-stage ring configuration. The proposed structure of delay cells and the start-up circuit were implemented using IBM 130 nm CMOS technology. The frequency can be tuned between 300 kHz and 11.57 MHz by varying the supply voltage from 0.35 to 0.9 V. An average current of 5.5 µA (2.5 µW) was consumed to generate rail-to-rail differential quadrature signals with a frequency of 2 MHz as the target operating point dedicated to low-power implantable transceivers.

CMOS QVCO With Current-Reuse, Bottom-Series Coupling, and Forward Body Biasing Techniques

This letter presents an LC-tank quadrature voltage-controlled oscillator (QVCO) using bottom-series coupling, forward body biasing, and current-reuse techniques. The bottom-series coupling to generate the quadrature signals enhances the phase noise performance. The forward body biasing of the switching and coupling transistors is used to alleviate the voltage headroom issue for stacked transistors. In addition, the current-reuse technique reduces the current consumption. A phase shift analysis for QVCOs introduces how to choose device sizes for a better Q-factor of the LC-tank. The proposed QVCO showed a phase-noise figure-of-merit of -190.9 dBc/Hz and a frequency tuning range from 5.80 to 6.44 GHz, while having a low power consumption of 2 mW for the core QVCO from a supply of 1.05 V.

Ultra‐low‐power quadrature VCO for 2.4 GHz‐band IEEE 802.15.4 standard

A fully integrated quadrature voltage-controlled oscillator (QVCO) for IEEE 802.15.4 transceivers is presented. The QVCO supports the 2.4 GHz unlicensed industrial, scientific and medical (ISM) band. The proposed QVCO generates 2.25–2.9 GHz covering 2.4 GHz transceivers. Quadrature coupling between the VCO cores is achieved using common source transistors which have their drains directly connected to the supply voltage. By using this structure, the effect of 1/f noise up-conversion in the phase-noise performance could be reduced. The QVCO achieves a measured phase noise of −116.74 dBc/Hz at 1 MHz offset with a centre frequency of 2.5 GHz. The proposed QVCO consumes 0.55 mW from a 0.45 V supply voltage and is implemented in a standard 0.13 μm CMOS process with a core area of 0.315 mm2.

A 6-GHz capacitively-coupled Colpitts CMOS quadrature voltage controlled oscillator

In this work a new low-noise low-power Colpitts quadrature voltage controlled oscillator (QVCO) made by coupling two identical current-switching differential Colpitts voltage controlled oscillators...

Design of low‐phase‐noise CMOS transformer‐based gate‐coupled quadrature VCO

A low-phase-noise transformer-based gate-coupled quadrature voltage-controlled oscillator (TGC-QVCO) using 0.13 μm CMOS technology is presented. The TGC-QVCO consumes 7 mW at 1 V power supply with 18% frequency tuning. The measured phase noise at 1 MHz offset varies from about −122 to −119 dBc/Hz for frequency tuning from 1.34 to 1.6 GHz. The achieved figure of merit (FoM) is 179 dB and the chip area is 800 × 900 μm2.

Indirect Back-Gate Coupling Quadrature LC-VCO

This letter presents a new quadrature voltage-controlled oscillator (QVCO), which consists of two p-core cross-coupled voltage-controlled oscillators (VCOs) using indirect back-gate coupling. In conventional direct-back coupling the resonator's voltage swing, tuning range, and quality factor are respectively limited by the forward-conducting back-gate junction cut-in voltage, diffusion capacitance and small dynamic resistance. To generate quadrature phase signals with strong coupling strength and large output swing, the proposed design uses pMOSFETs as buffers between the back-gate diode and LC tank to eliminate the drawback in existing back gate coupling QVCOs. The proposed CMOS QVCO has been implemented with the TSMC 0.18 μm SiGe 3P6M technology. At the supply voltage of 0.8 V, the total power consumption is 4.4 mW. The free-running frequency of the QVCO is tuneable from 5.96 GHz to 6.60 GHz as the tuning voltage is varied from 0.0 V to 0.8 V. The measured phase noise at 1 MHz frequency offset is -120.5 dBc/Hz at the oscillation frequency of 6.59 GHz and the figure of merit (FOM) of the proposed QVCO is -190.4 dBc/Hz.

A 57.9-to-68.3 GHz 24.6 mW Frequency Synthesizer With In-Phase Injection-Coupled QVCO in 65 nm CMOS Technology

A fully integrated 60 GHz frequency synthesizer with an in-phase injection-coupled quadrature voltage-controlled oscillator (IPIC-QVCO) is proposed. Through a particular symmetrical coupling network formed by diode-connected transistors, the in-phase coupling is realized in the IPIC-QVCO, which reduces both phase noise and phase error. A compact inductor-less divider chain is designed to reduce power consumption. A self-correcting low spur charge pump is employed to reduce reference spur. A standalone 60 GHz IPIC-QVCO and a fully integrated PLL are implemented in standard 65 nm low power CMOS technology. The measurement results show that the QVCO covers a frequency range from 57.88 to 68.33 GHz while consuming 11.4 mW power from a 1.2 V supply. The phase noise of the QVCO is -92 ~ -95 dBc/Hz at 1 MHz offset. The FOM and FOM T of the QVCO are -178.1 ~ -179.7 and -182.5 ~ -184.1 dBc/Hz respectively. The tuning range of the frequency synthesizer is from 57.9 to 68.3 GHz, and the power consumption is 24.6 mW. The phase noise of the frequency synthesizer is -89.8 ~ -91.5 dBc/Hz at 1 MHz offset across the frequency band.

A self-correcting quadrature voltage controlled oscillator

A self-correcting quadrature voltage controlled oscillator (QVCO) with phase correcting loop is proposed. It comprises the QVCO core and phase correcting loop, which corrects the quadrature phase error. Two LC VCOs, buffers, and phase shifters are coupled in circular configuration to achieve IQ symmetry. This paper introduces the idea of realizing QVCO with low phase noise and accurate quadrature phase by using the phase correcting loop. The simulation results based on the 65 nm CMOS process show that the self-correcting QVCO has a phase error less than 0.5° and 1 MHz offset phase noise of −120 dBc/Hz at 3.7 GHz with 49% tuning range.

Ultra‐low‐phase‐noise CMOS LC quadrature voltage controlled oscillator with Colpitts topology

A new low-phase-noise colpitts LC quadrature voltage controlled oscillator (QVCO) is presented. The proposed QVCO is realised by coupling two differential current-switching Colpitts oscillators in an ‘in-phase–anti-phase’ manner. The coupling technique between the two Colpitts LC-voltage controlled oscillators (VCOs) has significantly improved the phase noise of the proposed circuit without using any extra elements. The oscillation frequency of the proposed LC-QVCO is 4 GHz. The Colpitts QVCO exhibits a phase noise of −131.5 and −141.3 dBc/Hz at 1 and 3 MHz offset, respectively. By generalising the coupling scheme to more than two differential Colpitts VCOs in a loop, multiphase signals can be generated.

A Clock Gated Colpitts Cmos Quadrature Vco For Low Power Applications

A Clock Gated Colpitts Cmos Quadrature Vco For Low Power Applications

Low-power CMOS LC QVCO using zero-biased transistor coupling of MWCNT network-based VCO structure

This paper presents design, analysis and implementation of a 2.4GHz QVCO (Quadrature Voltage Controlled Oscillator), for low-power, low-voltage applications. Cross coupled LC VCO (Inductor–Capacitor Voltage Controlled Oscillator) topology realized using integration of a micro-scaled capacitor and a MWCNT (Multi-Wall Carbon Nano-Tube) network based inductor together with the CMOS circuits is utilized together with MOS transistors as coupling elements to realize QVCO. With the passive coupling achieved from the MOS transistors, power consumption is minimized while maintaining a small chip area. The variable capacitors and the inductors are designed using ANSYS and imported through DAC components in ADS (Advanced Design software). Accurate simulation of the QVCO is performed in the software environments and the results are provided. The measurement results show that the QVCO provides quadrature signals at 2.4GHz and achieves a phase noise of −130dBc/Hz 1MHz away from the carrier frequency. The VCO produces frequency tuning from 2.1GHz to 2.60GHz (20.83%) with a control voltage varying from 0 to 0.3V. It achieves a peak to peak voltage of 0.59V with an ultra low power consumption of 3.8mW from a 0.6V supply voltage. The output power level of the QVCO is −10dBm, with an improved quality factor of 45. The phase error of the QVCO is measured as 3.1°.

Low power current-mode voltage controlled oscillator for 2.4 GHz wireless applications

In this paper, a new Complementary Metal Oxide Semiconductor (CMOS) low power Quadrature Voltage Controlled Oscillator (QVCO) based on Chartered 0.18μm Radio frequency (RF) CMOS technology for 2.4GHz IEEE 802.11b Wireless Local Area Networks (WLAN) applications is presented. Two explicit quadrature outputs can be realized at high impedance terminals of the QVCO, and it can be cascaded directly to the next stage of a communication system without any matching conditions. The post-layout simulation results show that the oscillation frequency of the QVCO can be tuned from 1.8GHz to 2.4GHz by changing the control voltage.

Dual‐band quadrature voltage‐controlled oscillator using differential inner‐diamond‐structure switchable inductor

A dual-band quadrature voltage-controlled oscillator (QVCO) with high figure-of-merits (FOMs) and cost-area efficiency is presented by integrating with differential inner-diamond-structure switchable inductors which have improved performances. This proposed QVCO is fabricated in a 0.18-μm complementary metal-oxide semiconductor process with an active-region area of 0.61 mm2. The QVCO core totally consumes 6.8 mA from 1.8 V supply voltage. The frequency tuning ranges are 120 MHz (from 3.18 to 3.3 GHz) for the low-band and 500 MHz (from 6.94 to 7.44 GHz) for the high-band, while the tuning voltage rises from 0 to 1.8 V. The best phase noises with an offset frequency of 1 MHz from the oscillation frequency in the low- and high-bands are −121.9 and −117.5 dBc/Hz, respectively. The measured phase errors in both high-band and low-band are less than 1°. The calculated FOMs, no matter the switch is off or on, are better than −180 dBc/Hz.

Design Techniques for Load-Independent Direct Bulk-Coupled Low Power QVCO

Design techniques for a load-independent low-power low-phase-noise CMOS LC direct bulk-coupled quadrature voltage-controlled oscillator (DBC-QVCO) is presented in this paper. A capacitor tapping technique is used to lower the phase noise and achieve load-independent frequency of oscillation. Class-C operation is used to further reduce the phase noise and power consumption. Quadrature coupling is achieved using bulk coupling, leading to reduction in both power and area. The DBC-QVCO has been implemented in a standard 0.18-μm BiCMOS process and occupies an area of 0.3 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The implemented DBC-QVCO achieves a measured phase noise of -114.2 dBc/Hz at 1-MHz offset from the 6.26-GHz carrier while consuming only 3.2 mW from a 1-V power supply. The DBC-QVCO achieves a figure of merit (FOM) of -185.1 dBc/Hz and an FOM with area of -190.3 dBc/Hz, which are among the best compared with recently published QVCOs operating in a similar frequency range.

A 4.6 GHz cascade switched biasing LC–QVCO using source-body resistor

This paper presents a 4.6 GHz LC quadrature voltage-controlled oscillator (QVCO) in which the phase noise performance is improved by two methods: cascade switched biasing (CSB) technique and source-body resistor. The CSB topology can reduce the resonator loss caused by MOSFET resistance. Meanwhile, it can maintain the benefits of conventional switched biasing technique. The source-body resistors are utilized to reduce the noise contribution of the substrate related to the cross coupled MOSFETs. The proposed QVCO has been implemented in standard 0.18 μm CMOS technology. With the two methods mentioned above, it consumes 4.9 mW under 1 V voltage supply and achieves a phase noise of ?120.3 dBc/Hz at 1 MHz frequency offset from the carrier of 4.56 GHz. The figure of merit is 186.5 dBc/Hz and the tuning range is from 4.2 G to 5 GHz (17.3 %). When the QVCO operates at 0.8 V voltage supply, the power consumption is 2.88 mW and the phase noise is ?115.7 dBc/Hz at 1 MHz frequency offset from the carrier of 4.58 GHz.