Quadrature Oscillator Research Articles

A simple grounded FDNR and capacitance simulator based-on CCTA

This article purposes to present a simple grounded FDNR and capacitance simulator using CCTA. The proposed FDNR is very simple which consists of single CCTA and 2 grounded capacitors. As well, the FDNR values are easy to be adjusted by electronic tuning via DC bias current of CCTA. An application example as a low-pass filter and a quadrature oscillator are included to confirm the usability of the proposed FDNR. Moreover, the proposed FDNR can be changed to capacitance simulator by replacing a grounded capacitor with a grounded resistor. The band-pass filter as an example for using the capacitance simulator is included. The BJT technology and PSPICE simulation are designed and verified performance of the proposed circuit. The results are a good agreement to the theoretical anticipation.

Comparison of Two Solutions of Quadrature Oscillators With Linear Control of Frequency of Oscillation Employing Modern Commercially Available Devices

This paper proposes two circuits of frequency-controlled oscillators, whose structures are based only on simple commercially available active elements with minimum number of terminals, in particular, the differential voltage buffer, controllable voltage amplifier and electronically controllable current conveyor. Two methods for achieving linear control (tuning) of frequency of oscillations (FO) are discussed. The first method employs a simple structure. However, the generated signal level (amplitude) depends on the tuning process. This is a drawback of this method. The second method solves this drawback completely, and the generated signals have constant amplitudes during the tuning of FO. The expected behavior is confirmed by laboratory experiments utilizing commercially available high-speed active elements (current- and voltage-mode multipliers, video difference amplifier). Operational range was tested from frequencies of hundreds of kHz up to frequencies of tens of MHz.

New canonic lossy inductor using a single CDBA and its application

A new lossy inductor (parallel R-L type) using single current differencing buffered amplifier (CDBA) is presented, which employs only two resistors and a grounded capacitor. The proposed lossy inductor is shown to be useful in realizing an oscillator circuit, which provides quadrature voltage outputs using only two CDBAs, three resistors and two grounded capacitors and offers independent control on condition of oscillation and frequency of oscillation up to a frequency of 61 MHz. Detailed non-ideal analysis including single-pole model for voltage and current gain has also been carried out. SPICE simulation results and experimental results based upon the CDBA constructed from commercially available IC AD844 have been included which confirm the practical workability of the proposed lossy inductor and quadrature oscillator circuit.

A Blocker-Tolerant Current Mode 60-GHz Receiver With 7.5-GHz Bandwidth and 3.8-dB Minimum NF in 65-nm CMOS

A current-mode 60-GHz direct-conversion receiver, which can break performance tradeoffs among bandwidth, noise figure (NF), and linearity is designed and realized in 65-nm CMOS. The 60-GHz receiver employs the novel frequency-staggered series resonance common source (FSRCS) stage to extend RF bandwidth with superior noise performance. The receiver's current-mode operation offers excellent out-of-band blocker tolerance and linearity. With on-chip quadrature local oscillator generations, the fabricated receiver simultaneously achieves minimal NF of 3.8 dB, RF bandwidth of 7.5 GHz, output P1 dB of 1 dBm, and maximum conversion gain of 36 dB. The receiver is capable of tolerating out-of-channel blocker up to -9 dBm at 3.5 GHz away. It occupies a silicon area of 1.3 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and draws 25.5 mA of current from a 1-V supply.

An Alternative Method for PM Signal Generation and Detection

ABSTRACTThis paper presents a novel scheme for generating a phase modulated (PM) continuous wave carrier of constant envelope and the corresponding demodulation scheme. The modulator is based on the principle of the quadrature carrier multiplexing (QCM) wherein the sine wave carrier is multiplied by the message signal, m(t), and the cosine wave carrier is multiplied by the modified signal, √ (1–m2(t)), with the constraint that │m(t)│<1. The demodulator includes an amplitude limiter, a bandpass filter, and a coherent detector. The proposed scheme introduces a maximum linear phase shift of about ±20° when the message signal amplitude is 0.9 V. The phase shift introduced into the carrier is linear to the tune of ±360° as the message signal amplitude is reduced. The proposed scheme allows for the use of high-frequency stable quadrature oscillators in the modulator and offers better noise immunity like the conventional PM carrier. Furthermore, this paper presents a view point that the existing analogue modulation schemes can be viewed as special cases of the QCM principle.

Quadrature oscillators using two CFOAs and four passive components

Quadrature oscillators using two CFOAs and four passive components

Implementation of a wireless ECG acquisition SoC for IEEE 802.15.4 (ZigBee) applications.

This paper presents a wireless biosignal acquisition system-on-a-chip (WBSA-SoC) specialized for electrocardiogram (ECG) monitoring. The proposed system consists of three subsystems, namely, 1) the ECG acquisition node, 2) the protocol for standard IEEE 802.15.4 ZigBee system, and 3) the RF transmitter circuits. The ZigBee protocol is adopted for wireless communication to achieve high integration, applicability, and portability. A fully integrated CMOS RF front end containing a quadrature voltage-controlled oscillator and a 2.4-GHz low-IF (i.e., zero-IF) transmitter is employed to transmit ECG signals through wireless communication. The low-power WBSA-SoC is implemented by the TSMC 0.18-μm standard CMOS process. An ARM-based displayer with FPGA demodulation and an RF receiver with analog-to-digital mixed-mode circuits are constructed as verification platform to demonstrate the wireless ECG acquisition system. Measurement results on the human body show that the proposed SoC can effectively acquire ECG signals.

Robustness Enhancement of a Class-C Quadrature Oscillator Using Capacitive Source Degeneration Coupling

This brief presents a low-phase-noise Class-C-type quadrature voltage-controlled oscillator (QVCO) with a robust start-up. The chip was implemented using the 0.18- $\mu\hbox{m} $ CMOS technology. A source degeneration coupling technique is used to generate quadrature signals and enables the elimination of bimodal oscillation. Capacitive degeneration coupling also provides negative impedance to compensate for losses in the $LC$ tank, resulting in less power consumption in the core circuit to sustain oscillation. The proposed 2.4-GHz QVCO design achieves a 13.46% tuning range and a phase noise of $-$ 128.65 dBc/Hz at a 1-MHz offset while only consuming 2.67 mW from a 1.8-V supply. The oscillator demonstrated robust operation from $-$ 25 $^{\circ}\hbox{C}$ to 85 $^{\circ}\hbox{C}$ with phase noise lower than $-$ 122 dBc/Hz at a 1-MHz offset. The proposed QVCO achieves a remarkable figure of merit of $-$ 192 dBc/Hz.

Novel Third-Order Quadrature Oscillators with Grounded Capacitors

This paper presents two Current Differencing Transconductance Amplifiers (CDTA)-based current-mode resistors-less variable frequency third-order Quadrature Oscillators (TOQO). The proposed TOQOs consist of minimum number of active and passive components, especially the first TOQO, only two CDTAs and three capacitors are used in it. The two TOQOs are completely resistor-less, and the capacitors used in the TOQOs are all grounded, which are ideal for monolithic integration. The condition of oscillation (CO) and frequency of oscillation (FO) of the TOQOs can be controlled electronically and independently, which make them suitable for variable frequency oscillator (VFO). Moreover, the two TOQOs can provide four explicit quadrature current outputs at high output impedance terminals, and they can be directly cascaded with other current-mode circuits without any impedance matching requirements. Cadence IC Design Tools 5.1.41 post-layout simulation results and experimental evidence are included to confirm all the theory.

CCCCTA-based resistorless voltage and current mode quadrature oscillator

CCCCTA-based resistorless voltage and current mode quadrature oscillator

New Single VDCC-based Explicit Current- Mode SRCO Employing All Grounded Passive Components

This paper proposes a new single resistancecontrolled sinusoidal oscillator (SRCO) which employs only onevoltage differencing current conveyor (VDCC), two groundedresistors and two grounded capacitors. The presented circuitconfiguration offers the following advantageous features (i)explicit current-mode output with independent control ofcondition of oscillation (CO) and frequency of oscillation (FO) (ii)low active and passive sensitivities and (iii) a very good frequencystability. The proposed structure can also be configured as (a)trans-admittance low pass filter and band pass filter and (b)quadrature oscillator. The validity of the proposed SRCO,quadrature oscillator and trans-admittance low pass filter andband pass filter has been verified by PSPICE simulations usingTSMC CMOS 0.18μm process model parameters.

CMOS 스위치부를 갖는 L-대역 단측파대역 주파수 혼합기 및 C-대역 QVCO 설계 및 제작

CMOS 스위치부를 이용해 출력주파수의 상/하향 변환을 제어하는 L-대역용 단측파 대역 주파수 혼합기 회로(mixer)와 C-대역용 쿼드러쳐 전압 제어발진기(QVCO)를 제안하고 TowerJazz 사의 0.18 um RFCMOS 공정을 사용하여 설계 및 제작하였다. 제안된 주파수혼합기의 L대역 출력 특성은 변환이득 6.6~7.5 dB, 이미지 제거비 70 dBc, 단자간 격리도 65 dBc 이다. 전압 제어 발진기는 6.2~6.7 GHz 의 주파수 튜닝 범위에서 4 dBm 의 출력전력을 공급한다. 공급전압은 1.8 V이며, 주파수 혼합기 중심부와 스위치에 공급되는 총 전류는 36 mA, 전압 제어 발진기에 공급되는 총 전류는 23 mA 이다. An L-band single side band(SSB) mixer with CMOS switches and a C-band quadrature voltage-controlled oscillator(QVCO) have been developed using the TowerJazz 0.18-um RFCMOS process. The SSB mixer exhibits a conversion gain of 6.6 ~ 7.5 dB with a 70-dBc image rejection ratio and 65-dBc port isolation. The oscillation frequency range of the QVCO is 6.2 ~ 6.7 GHz with an output power of 4~6 dBm. For measurement, 1.8 V supply voltage is used while drawing 36 mA for the mixer and 23 mA for the QVCO.

Low‐voltage quadrature LC oscillator with fast start‐up

A novel low-voltage quadrature inductor–capacitor (LC) oscillator is presented. The proposed oscillator is immune to the phase ambiguity problem encountered in quadrature oscillators. Simulations show that the proposed oscillator can obtain a phase noise of −150 dBc/Hz at 10 MHz offset for a 5 GHz centre frequency and a figure-of-merit (FoM) of 195 dBc/Hz. The proposed oscillator has a superior start-up performance compared to other low-voltage quadrature LC oscillator architectures.

An Ultra-Low Power QVCO Using Current-Coupling and Bulk-Injection Techniques

In this letter, a quadrature voltage-controlled oscillator (QVCO) using PMOS transistors to couple two VCO cores is presented. The power consumption is drastically reduced by using the bulk of the PMOS transistors to lower the transconductance of both differential pairs in the coupling network. The QVCO achieves a measured phase noise of ${-}116.02$ dBc/Hz at 1 MHz offset and a quadrature phase error of 0.48 $^{\circ}$ with a center frequency of 3.5 GHz. The proposed QVCO consumes 230 $\mu$ W from a 0.45 V supply voltage. The QVCO is implemented in a standard 0.13 $\mu$ m CMOS process with core area of 0.315 mm $^{2}$ .

Low voltage low-phase-noise SB-QLCO using second harmonics coupling technique

A switched biasing quadrature oscillator with LC tanks (SB-QLCO) is proposed to achieve low voltage and low phase noise. In this work, coupling devices, capacitors, don’t contributes any noise and this second harmonics coupling technique leads to low voltage. The proposed QLCO was simulated in 0.18 μm CMOS process. Simulating results showed a phase noise of −126 dBc/Hz at an offset of 1 MHz and a phasenoise figure of merit of 193 dB while consuming 6 mA from a 0.8 V power supply.

Differential rail‐to‐rail voltage‐controlled quadrature ring oscillator for low‐power implantable transceivers

A new low-power rail-to-rail voltage-controlled quadrature oscillator is presented. This oscillator was implemented to provide the frequency deviation of frequency-shift-keying (FSK) modulation in implantable radio-frequency (RF) transceivers. The quadrature oscillator circuit generates differential in-phase and quadrature-phase (I and Q) signals in a two-stage ring configuration. The proposed structure of delay cells and the start-up circuit were implemented using IBM 130 nm CMOS technology. The frequency can be tuned between 300 kHz and 11.57 MHz by varying the supply voltage from 0.35 to 0.9 V. An average current of 5.5 µA (2.5 µW) was consumed to generate rail-to-rail differential quadrature signals with a frequency of 2 MHz as the target operating point dedicated to low-power implantable transceivers.

A 0.137 mm$^{{2}}$ 9 GHz Hybrid Class-B/C QVCO With Output Buffering in 65 nm CMOS

A compact realization of hybrid class-B/C quadrature voltage-controlled oscillator (QVCO) with output buffering is proposed. It employs a four-phase amplitude detector feedback loop to shift the operation mode from hybrid class-B/class-C to class-C after power up. The power-efficient class-C core allows quadrature-locking via passive capacitive coupling, whereas the auxiliary class-B core ensures a robust startup. For higher output drivability, PMOS-based source followers are stacked atop the QVCO for reusing its bias current and avoiding any AC-coupling networks. The buffered QVCO can directly drive up the 50- Ω port of testers, or to withstand a large capacitive load in on-chip signal distribution. The fabricated 9 GHz QVCO in 65 nm CMOS draws 10.5 mW and exhibits -99.37-dBc/Hz phase noise at 1 MHz offset. The active area is just 0.137 mm 2 by using two compact spiral inductors with patterned ground shields.

Inside view

inside view

Current-mode current-tunable four-phase quadrature oscillator

A current-mode current-tunable four-phase quadrature oscillator (QO) using current differencing transconductance amplifiers (CDTA) is presented in this paper. The proposed QO consists of three CDTAs and two grounded capacitors, which can provide four quadrature current outputs at high impedance nodes. The proposed QO has the advantages of electronically and independently control of oscillation condition and oscillation frequency. Moreover, the active and passive sensitivities of the QO are low. Cadence IC Design Tools 5.1.41 post-layout simulation results are included to confirm the theory.

CMOS QVCO With Current-Reuse, Bottom-Series Coupling, and Forward Body Biasing Techniques

This letter presents an LC-tank quadrature voltage-controlled oscillator (QVCO) using bottom-series coupling, forward body biasing, and current-reuse techniques. The bottom-series coupling to generate the quadrature signals enhances the phase noise performance. The forward body biasing of the switching and coupling transistors is used to alleviate the voltage headroom issue for stacked transistors. In addition, the current-reuse technique reduces the current consumption. A phase shift analysis for QVCOs introduces how to choose device sizes for a better Q-factor of the LC-tank. The proposed QVCO showed a phase-noise figure-of-merit of -190.9 dBc/Hz and a frequency tuning range from 5.80 to 6.44 GHz, while having a low power consumption of 2 mW for the core QVCO from a supply of 1.05 V.