Quadrature Bandpass Sigma-delta Modulator Research Articles

A 1-MHz-Bandwidth Gm-C-Based Quadrature Bandpass Sigma-Delta Modulator Achieving −153.7-dBFS/Hz NSD With Background Calibration

This paper presents a fifth-order continuous-time Gm-C-based quadrature bandpass sigma-delta ( $\Delta \Sigma$ ) modulator for Internet-of-Things applications. In the presented $\Delta \Sigma $ modulator, a reconfigurable full-scale input amplitude assists the $\Delta \Sigma $ modulator, achieving a wide dynamic range (DR) and a low-noise floor. A following system-level supply voltage and temperature background tracking technique stabilizes the frequency response of the Gm-C-based quadrature bandpass $\Delta \Sigma $ modulator. Furthermore, the 1.5-bit feedback current DAC employs a PN-based semi-self-swapping logic to relax the matching requirement. The prototype $\Delta \Sigma $ modulator was fabricated in a 180-nm CMOS process with an active area of 0.28 mm2. The $\Delta \Sigma $ modulator achieves a total DR of 93.7 dB with the reconfigurable full-scale input amplitude, resulting in a noise spectral density of −153.7 dBFS/Hz with a bandwidth of 1 MHz. The presented $\Delta \Sigma $ modulator consumes 2.0 mW with a power supply of 1.8 V and a sampling frequency of 32 MHz.

Design and implementation of quadrature bandpass sigma-delta modulator used in low-IF RF receiver * * Project supported by the National Natural Science Foundation of China (Nos. 61471245, U1201256), the Guangdong Province Foundation (No. 2014B090901031), and the Shenzhen Foundation (Nos. JCYJ20160308095019383, JSGG20150529160945187).

This paper presents the design and implementation of quadrature bandpass sigma-delta modulator. A pole movement method for transforming real sigma-delta modulator to a quadrature one is proposed by detailed study of the relationship of noise-shaping center frequency and integrator pole position in sigma-delta modulator. The proposed modulator uses sampling capacitor sharing switched capacitor integrator, and achieves a very small feedback coefficient by a series capacitor network, and those two techniques can dramatically reduce capacitor area. Quantizer output-dependent dummy capacitor load for reference voltage buffer can compensate signal-dependent noise that is caused by load variation. This paper designs a quadrature bandpass Sigma-Delta modulator for 2.4 GHz low IF receivers that achieve 69 dB SNDR at 1 MHz BW and -1 MHz IF with 48 MHz clock. The chip is fabricated with SMIC 0.18 μm CMOS technology, it achieves a total power current of 2.1 mA, and the chip area is 0.48 mm2.

Correction to “A 2.7 mW, 90.3 dB DR Continuous-Time Quadrature Bandpass Sigma-Delta Modulator for GSM/EDGE Low-IF Receiver in 0.25 $\mu$m CMOS” [Mar 09 891-900

In the above titled paper (ibid., vol. 44, no. 3, pp. 891-900, Mar 09), an error was made in Fig. 15. The corrected figure is presented here.

A 2.7 mW, 90.3 dB DR Continuous-Time Quadrature Bandpass Sigma-Delta Modulator for GSM/EDGE Low-IF Receiver in 0.25 $\mu$m CMOS

Quadrature bandpass SigmaDelta modulators based on polyphase filters are suited for analog-to-digital conversion in GSM/EDGE low-IF receivers. This paper presents a continuous-time quadrature bandpass sigma-delta (SigmaDelta) modulator with a chain of integrators with weighted capacitive feedforward summation (CICFF) topology - which is a desirable solution for implementation in low power applications. A new compensation scheme for the polyphase filter is proposed. The summation of feedforward signals is implemented by weighted capacitors, without the necessity of any additional active components. The effectiveness of the proposed architecture is proved on a test chip which was designed in a standard 0.25 mum CMOS technology. The designed SigmaDelta modulator has a power consumption of 2.7 mW at 1.8 V supply voltage, a dynamic range of 90.3 dB and a peak SNDR of 86.8 dB. The chip area is 0.5 times 1.4 mm2 including pads.

A Polyphase Filter Design for Continuous-Time Quadrature Bandpass Sigma–Delta Modulators

This paper presents a strategy for successful polyphase-filter design for continuous-time quadrature bandpass sigma-delta (SigmaDelta) modulators. Based on a low-pass filter with a chain of integrators with weighted capacitive feedforward summation (CICFF) topology - which is suited for implementation in low-power applications - analytical equations are derived. A new compensation scheme is proposed and implemented by cross-coupling additional resistors, without the necessity of extra-active components. Translation to intermediate frequency in second- and fourth-order polyphase filters with the proposed compensation scheme are compared to analytical considerations and simulation. Nonlinearities introduced by mismatch of feedforward coefficients and finite gain-bandwidth of amplifiers are considered.

Mismatch Insensitive Double-Sampling Quadrature Bandpass $\Sigma\Delta$ Modulation

In a double-sampling quadrature bandpass sigma-delta modulator, path mismatch between the double-sampling branches and between the I/Q paths occurs. In this paper, an analytical study is presented which shows that this causes quantization noise and input signals to fold from the image band into the signal band and that this also results in a self-image component. To reduce the folding from the image band, a novel resonator is presented. This resonator has a bilinear input circuit so that noise and signals exhibits first-order shaping before folding in the band of interest. Next, three different modulator architectures based on the novel resonator are introduced. Finally, the remaining problem of self-image is tackled with a simple, yet efficient offline calibration strategy. Various design examples are shown and simulated to illustrate and prove the effectiveness of the proposed architectures and methods.

Quadrature /spl Sigma//spl Delta/ modulators with a dynamic element matching scheme

This paper presents a new topology of a multibit quadrature bandpass sigma-delta modulator which employs a simple dynamic element matching (DEM) technique in order to reduce the effects of path mismatch, namely aliasing in the signal band of the mirror images of the signal and of the quantization noise. The DEM scheme results in a reduction of the aliasing of the quantization noise mirror image while it reduces the input signal mirror image alias problem to a self-image problem. It is shown that the self-image can be completely removed in switched-capacitor implementations by using the same capacitors to sample the input and the reference of the feedback digital-analog converters (DACs). Moreover, a simple method for extending low-pass mismatch noise shaping techniques to the complex bandpass case is proposed for the case of multibit feedback DACs.

A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers

This paper presents a quadrature bandpass /spl Sigma//spl Delta/ modulator with continuous-time architecture. Due to the continuous-time architecture and the inherent anti-aliasing filter, the proposed /spl Sigma//spl Delta/ modulator needs no additional anti-aliasing filter in front of the modulator in contrast to quadrature bandpass /spl Sigma//spl Delta/ modulators with switched-capacitor architectures. The second-order /spl Sigma//spl Delta/ modulator digitizes complex analog I/Q input signals at 1-MHz intermediate frequency and operates within a clock frequency range of 25-100 MHz. The modulator chip achieves a peak signal-to-noise-distortion ratio (SNDR) of 56.7 dB and a dynamic range of 63.8 dB within a 1-MHz signal bandwidth and at a clock frequency of 100 MHz. Furthermore, it provides an image rejection of at least 40 dB. The 0.65-/spl mu/m BiCMOS chip consumes 21.8 mW at 2.7-V supply voltage.