A 1/fγ drain current noise model for deep-submicron MOSFETs with ultrathin oxide is presented. Based on the number and correlated mobility fluctuation mechanisms, the model is derived incorporating a tunneling assisted-thermally activated process and a more realistic trap distribution inside the gate oxide layer. The effects of the device structure and processing technologies on the noise characteristics are taken into consideration through a quadratic mobility degradation factor, a parasitic resistance, a doping profile, and trap-related parameters. For ultrathin oxide MOSFETs, the trapping efficiency ratio and the scattering rate are expressed in terms of the trap distance and the inversion carrier density, enabling an accurate prediction of the noise behavior. From quantitative results simulated with extracted data, it is shown that the new model is applicable to design future CMOS devices and new device processing technologies, and is suitable to be implemented in circuit simulators.