Push-push Voltage-controlled Oscillator Research Articles

A 267 GHz Wide Tuning Range VCO With −3.5 dBm Peak Output Power in 40-nm CMOS

This article presents a highly efficient, wide tuning range push-push voltage-controlled oscillator (VCO) in the sub-terahertz frequency band. The proposed VCO adopted a novel capacitance-splitting feedback technique to achieve high oscillation frequency and output power. The frequency tuning is provided through a tunable source degeneration (TSD) network. The proposed TSD network enables a wide tuning range without substantially sacrificing output power. The proposed VCO is fabricated in a 40-nm complementary metal-oxide-semiconductor (CMOS) process and has a peak output power of −3.5 dBm, a center frequency of 267.2 GHz, and a continuous tuning range of 27 GHz. The VCO consumes 30 mA current from a 1.1 V dc supply, resulting in 1.35% dc-to-RF efficiency.

W- and G-Band GaN Voltage-Controlled Oscillators With High Output Power and High Efficiency

This article presents W- and G-band voltage-controlled oscillators (VCOs) fabricated in a 60 nm GaN high electron-mobility transistor (HEMT) process with f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> /f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAX</sub> of 190/250 GHz. Two W-band fundamental VCOs (VCO1 and VCO2) are designed without and with a varactor, respectively. In addition, a G-band push-push VCO (VCO3) is designed to demonstrate feasibility of a GaN power source in the sub-terahertz band. The measurement shows that VCO1 and VCO2 exhibit output power of 22.5 and 22.6 dBm and dc-to-RF efficiency of 14.7% and 16.8% at 87.5 and 86.5 GHz, respectively. The power and efficiency are the highest values among the previously reported GaN VCOs operating beyond 50 GHz. Furthermore, VCO2 achieves a wide tuning range of 9.0 GHz (77.5-86.5 GHz). The VCO3 exhibits high output power of 9.3 dBm at 180.6 GHz. To the best of the authors' knowledge, this is the first demonstration of a G-band VCO in a GaN technology. The W- and G-band VCOs occupy compact chip areas of 0.48 and 0.32 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively.

D-Band Frequency Quadruplers in BiCMOS Technology

This paper presents two D-band frequency quadruplers (FQs) employing different circuit techniques. First FQ is a 129–171-GHz stacked Gilbert-cell multiplier using a bootstrapping technique, which improves the bandwidth and the conversion gain with respect to the conventional topology. Stacked architecture enables current reuse for the second frequency doubler resulting in a compact and energy-efficient design. The circuit reaches 3-dB bandwidth of 42 GHz, which is the highest among similar reported quadruplers. It achieves 2.2-dBm saturated output power, 5-dB peak conversion gain, and 1.7% peak DC-to-RF efficiency. The stacked FQ occupies 0.08 mm2 and consumes 22.7 mA from 4.4-V supply. Second presented circuit is a transformer-based injection-locked FQ (T-ILFQ) employing an E-band push–push voltage-controlled oscillator (PP-VCO). The VCO is a self-buffered common-collector Colpitts oscillator with a transformer formed on emitter inductors. Proposed configuration does not reduce the tuning range of the VCO, thus providing wide locking range and high sensitivity with respect to the injected signal. The T-ILFQ achieves 21.1% locking range, which is the highest among other reported injection-locked frequency multipliers. The peak output power is −4 dBm and the input sensitivity reaches −22 dBm. The circuit occupies 0.09 mm2 and consumes 14.8 mA from 3.3-V supply.

A 152-GHz OOK Transmitter With 3-dBm Output Power in 65-nm CMOS

A high output power 152 GHz ON-OFF keying transmitter in 65-nm CMOS is presented. The transmitter consists of a high dc-RF efficiency push-push voltage-controlled oscillator followed by a high-speed and high-gain switched-mode power amplifier. The transmitter achieves the highest output power (3 dBm) beyond 140 GHz in silicon process, with high on-off ratio (>39 dB) and high dc-RF efficiency (3.7%). The transmitter could support 10-Gb/s data rate communication with a bit-error rate of less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> .

Ka‐band VCO with parasitic capacitance cancelling technique

A Ka-band push-push voltage-controlled oscillator (VCO) using a parasitic capacitance cancelling technique is presented. To enhance the oscillation frequency ( f osc ) and the tuning range (TR), the parasitic capacitance of the VCO is cancelled with negative capacitance (NC). To realise NC, a negative impedance circuit (NIC) is analysed and designed. Because of self-resonance frequency, NC is realised using an open-circuit stable NIC. For further enhancement of the f osc , the VCO is developed in a push-push operation. The proposed VCO is fabricated in a commercial 0.15 μm GaAs pHEMT process. It shows 12.4% of the TR at 31.6 GHz with 11 dBm output power. With the NIC, the centre frequency of the VCO increases from 20.1 to 31.6 GHz and the TR increases from 5.7 to 12.4% compared with a VCO without the NIC.

Two 122-GHz Phase-Locked Loops in 65-nm CMOS Technology

Two 122-GHz phase-locked loops (PLLs) have been developed based on a 65-nm Si CMOS technology, and their performances are compared. For the first PLL, a voltage-controlled oscillator (VCO) with a frequency doubler embedded in the oscillator core was employed (PLL1), while the second PLL employs a push-push VCO (PLL2). The output powers of PLL1 and PLL2 were −8.6 and −21.9 dBm near 122 GHz, obtained from dc power dissipation of 82.9 and 87.7 mW, respectively. The respective locking ranges were measured to be 121.9–122.2 and 122.7–122.9 GHz for PLL1 and PLL2. The in-band phase noises were −59.2 and −60.1 dBc/Hz at 10-kHz offset, and the out-band phase noises were −102.4 and −99.5 dBc/Hz at 10-MHz offset for PLL1 and PLL2, respectively. The chip sizes were $1000 \times 760 ~\mu \text{m}^{2}$ (PLL1) and $1300 \times 840 ~\mu \text{m}^{2}$ (PLL2) including probing pads.

A V-Band Push-Push VCO With Wide Tuning Range Using &lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$0.18~\mu{\rm m}$&lt;/tex&gt;&lt;/formula&gt; CMOS Process

A V-band push-push voltage-controlled oscillator (VCO) with wide tuning range implemented in the $0.18~\mu{\rm m}$ CMOS process technology is presented in this letter. The output signal with frequency twice that of the VCO core is extracted from the center tap of inductors rather than the one-quarter wavelength transmission line. The measured oscillating frequency of the VCO is from 67.18 to 74.84 GHz corresponding to a 10.79% tuning range. At the 74.84 GHz output frequency, the measured phase noises at 1 MHz and 10 MHz frequency offsets are $-74.83~{\rm dBc/Hz}$ and $-102.53~{\rm dBc/Hz}$ , respectively. The core circuit draws a 13.5 mA current from a 1.8 V power supply.

A low-phase-noise Ka-band push-push voltage-controlled oscillator using CMOS/glass-integrated passive device technologies.

In this paper, a Ka-band CMOS push-push voltage- controlled oscillator (VCO) integrated into a glass-integrated passive device (GIPD) process is presented. The transformer, λ/4 transmission line, and inductors of the VCO are realized in the GIPD process, achieving superior performances, and therefore improve the phase noise of the VCO. Moreover, the transformer-based VCO is a differential Hartley topology to further reduce the phase noise and chip area. Operating at 1.8 V supply voltage, the VCO core consumes merely 3.8 mW of dc power. The measured phase noise is -109.18 dBc/Hz at 1 MHz offset from the 30.84 GHz oscillation frequency. The push-push VCO also demonstrates a 24.5 dB fundamental rejection, and exhibits an 8.4% tuning range. Compared with recently published CMOS-based VCOs, it is observed that the proposed VCO exhibits excellent performance under low power consumption.

A 200-GHz Inductively Tuned VCO With $-$7-dBm Output Power in 130-nm SiGe BiCMOS

A highly efficient push-push voltage-controlled oscillator (VCO) with a new inductive frequency tuning topology for (sub) terahertz frequencies is presented. The tuning technique is based on a variable inductance seen at the emitter node of a base-degenerated transistor. The variable inductor exhibits high quality factor and high tuning range due to the tunable transistor transconductance via bias current. Fabricated in a 0.13- μm SiGe BiCMOS process, the VCO achieves a tuning range of 3.5% and an output power of -7.2 dBm at 201.5 GHz. The dc power consumption of the VCO is 30 mW, resulting in a high dc to RF power efficiency of 0.6% and a figure of merit (FoMT) of -165, which is the highest FoM for any silicon-based VCO reported to date at this frequency range. To demonstrate the functionality of the tuning technique, three VCO prototypes at different oscillation frequencies, including one operating in the 222.7-229-GHz range, are implemented and measured.

A Study of SiGe HBT Signal Sources in the 220–330-GHz Range

The paper presents design optimization strategies and a comparison of the performance of SiGe HBT fundamental and push-push Colpitts and Colpitts-Clapp voltage-controlled oscillators (VCOs), with and without doublers and buffers, as possible solutions for efficient milliwatt-level, low-noise signal sources at submillimeter-wave frequencies. The fundamental frequency Colpitts VCO covers a 12% tuning range between 218 and 246 GHz (the highest for SiGe HBTs) with up to -3.6-dBm output power and 0.8% efficiency. The 300-GHz signal source, consisting of a Colpitts-Clapp VCO followed by a buffer amplifier and a doubler, shows -1.7-dBm output power around 290 GHz, -101-dBc/Hz phase noise at 10-MHz offset, 7.5% tuning range, and 0.4% efficiency. Finally, the push-push Colpitts-Clapp VCO exhibits the highest operation frequency, from 309 to 325 GHz, but with reduced efficiency of only 0.07% and 5% tuning range. It was concluded that the differential cascode buffer placed between the VCO and doubler was instrumental in achieving the best phase noise and output power with good efficiency and without compromising tuning range.

A low-power technique to boost the output amplitude of multi gigahertz push-push LC VCOS

A design technique to increase the output amplitude and hence the output power of push-push LC-based voltage-controlled oscillators (LC VCOs) is presented that relies on LC resonance boosting of the second harmonic. Measurement results are in good agreement with the results predicted from the analysis. Using the proposed technique, a low-power push-push LC VCO is designed and implemented in 90-nm CMOS. Based on the measurement results, the VCO has a frequency tuning range of 23%, from 20.1 to 24.8 GHz. It exhibits up to 8 dB improvement in its output power at the middle of the frequency band compared to a traditional push-push VCO. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:1581–1584, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27599

A CMOS Bidirectional 32-Element Phased-Array Transceiver at 60 GHz With LTCC Antenna

Fully integrated 32-element symmetrical TX/RX 60-GHz RF integrated circuit (RFIC) with built-in self-test is presented. The RF bidirectional power-combining architecture with shared blocks and less than 1-dB millimeter-wave transmit/receive (T/R) switch loss achieves record size and power consumption. The RFIC features an 8-dB noise figure and - 28-dBm IP1 dB in RX mode, 10-dB power gain, and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i> <b xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</b> of +3.5 dBm per chain in TX mode. Further included are a 2-bit phase shifter, an IF converter to/from 12 GHz, and an integrated frac- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> synthesizer with push-push voltage-controlled oscillator having a-93 dBc@1-MHz phase noise at 48-GHz local oscillator port. A novel high dynamic range phase and power detector is presented with 2° and ±1-dB accuracy over PVT in phase and power. A detailed analysis of both phase quantization and power distribution is presented. Array impairments such as mismatch and coupling were compared for different topologies. The RFIC is packaged on alumina for testing and on low-temperature co-fired ceramic (LTCC) for antenna integration. The 6 × 6 patch antenna on LTCC including four dummies achieves a gain of 19 dBi with scanning of ± 30°. The total root mean square amplitude and phase error of the array is 0.8 dB and 6 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> , respectively, resulting in a maximum array beam degradation of 1.4 dB for 2-bit quantization. The RFIC area is 29 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and it consumes 1.2 W/0.85 W at TX/RX, with a 29-dBm effective isotropic radiated power at -19-dB error vector magnitude.

A 20GHz Push-Push Voltage-Controlled Oscillator Using Second-Harmonic Peaking Technique for a 60GHz Frequency Synthesizer

This paper presents a 20 GHz push-push VCO realized by a 10 GHz super-harmonic coupled quadrature oscillator for a quadrature 60 GHz frequency synthesizer. The output nodes are peaked by a tunable second harmonic resonator. The proposed VCO is implemented in 65 nm CMOS process. It achieves a tuning range of 3.5 GHz from 16.1 GHz to 19.6 GHz with a phase noise of −106 dBc/Hz at 1 MHz offset. The power consumption of the core oscillators is 10.3 mW and an FoM of −181.3 dBc/Hz is achieved. key words: low phase noise, low power, tail-current modulation, impulse sensitivity function, super-harmonic coupled QVCO, push-push VCO

245-GHz LNA, Mixer, and Subharmonic Receiver in SiGe Technology

A four-stage common-base (CB) 245-GHz low-noise amplifier (LNA) and a fourth subharmonic 245-GHz transconductance mixer are presented. An integrated subharmonic receiver for sensing applications in the 245-GHz industrial-scientific-medical band is proposed. The receiver consists of a single-ended CB LNA, a fourth transconductance subharmonic mixer, a 60-GHz push-push voltage-controlled oscillator with a 1/32 divider, and an IF amplifier. It is fabricated in an SiGe: C BiCMOS technology with f T and fmax of 300 and 500 GHz, respectively. Its measured single-ended gain is 21 dB at 243 GHz with a tuning range of 12 GHz, and a noise figure of 33 dB. The input 1-dB compression point is -37 dBm . The receiver dissipates at 358 mW.

A Push-Push VCO With 13.9-GHz Wide Tuning Range Using Loop-Ground Transmission Line for Full-Band 60-GHz Transceiver

A 59-GHz push-push voltage-controlled oscillator (VCO)-based on 0.18m SiGe BiCMOS technology-for a full-band 60-GHz transceiver was developed. The VCO uses a loop-ground transmission line (LG-TML) composed of λf0/2 signal lines (half wavelength at fundamental frequency) and λ2f0/4 secondary lines (quarter wavelength at second harmonic frequency). The LG-TML makes it possible to output both a large signal at second harmonic frequency and an adequate signal at the fundamental frequency for driving a prescalar, while it prevents the Miller effect of the HBTs in the VCO from increasing and negative conductance from being reduced. As a result, the VCO achieves high output power of +1.5 dBm, while maintaining wide tuning range of 13.9 GHz (26% of the center oscillation frequency). Moreover, it exhibits a low phase noise of -108 dBc/Hz at a 1-MHz offset frequency and achieves a state-of-the-art figure of merit (FOMT) of -189.6 dB.

A LOW POWER PUSH-PUSH DIFFERENTIAL VCO USING CURRENT-REUSE CIRCUIT DESIGN TECHNIQUE

This paper presents a complementary metal-oxide- semiconductor (CMOS) difierential voltage-controlled oscillator (VCO) implemented with the push-push principle. The push-push VCO uses two frequency doublers stacked in series with an LC quadrature voltage-controlled oscillator (QVCO) to share the dc current with the QVCO for low power consumption. The proposed CMOS VCO has been implemented with the TSMC 0.18m CMOS technology, and the die area is 0:822£1:564mm 2 . At the supply voltage of 0.9V, the total power consumption is 3.15mW. The free-running frequency of VCO is tunable from 10GHz to 11.15GHz as the tuning voltage is varied from 0.0V to 1.2V. The measured phase noise at 1MHz frequency ofiset is i114:93dBc/Hz at the oscillation frequency of 9.99GHz, and the flgure of merit (FOM) of the proposed VCO is i190:0dBc/Hz.

Microstrip Square Open Loop Metamaterial Resonator and Rat Race Coupler for Low Phase Noise Push-Push VCO

In this paper, a novel low phase noise voltage-controlled oscillator (VCO) using metamaterial structure and rat race coupler is presented for reducing the phase noise without the reduction of the frequency tuning range. The metamaterial structure has been realized by microstrip square open loop double split ring resonator (SRR). The rat race coupler shows slightly higher transmission compared to a Wilkinson combiner and is, therefore, used instead to improve the performances of VCO. By providing these unique modifications, the proposed push-push VCO has a phase noise of -126.30~-124.83 dBc/Hz at 100 kHz in the tuning range of 5.672~5.800 GHz.

A fully integrated w-band push-push CMOS VCO with low phase noise and wide tuning range

A circuit topology suitable for a low-phase-noise wide-tuning-range push-push voltage-controlled oscillator (VCO) is proposed in this paper. By applying varactors connected between drain and source terminations of the cross-coupled pair, the tuning range is effectively increased and the phase noise is improved. Moreover, a small capacitor is inserted between the VCO core and testing buffer to reduce loading effects on the VCO core. Furthermore, the enhanced second-harmonic output signal is extracted at middle of the varactors, leading to the elimination of RF choke at VCO's second-harmonic output port and a reduced chip size. Based on the proposed architecture, this VCO fabricated in 0.18-μm CMOS exhibits a measured 6.35% tuning range. Operating at a supply voltage of 1.2 V, the VCO core consumes 7.5-mW dc power, and the measured phase noise is -75 dBc/Hz and -91.5 dBc/Hz at 100-kHz and 1-MHz offsets from the 77.8-GHz carrier, respectively. Compared with previously published silicon-based VCOs over 70 GHz, this work can simultaneously achieve low phase noise, wide tuning range, and low dc power consumption, leading to a superior figure of merit (FOM), and better figure of merit considering the tuning range (FOM(T)). In addition, this fully integrated VCO also demonstrates the highest operation frequency among previously published 0.18-μm CMOS VCOs.

Design of a Dual W- and D-Band PLL

This paper describes the design considerations and performance of the highest frequency phase-locked loop (PLL) reported to date. The PLL was fabricated in a 0.13-μm SiGe BiCMOS process and integrates on a single die: a fundamental-frequency 86-92 GHz Colpitts voltage-controlled oscillator (VCO), a differential push-push 160-GHz Colpitts VCO with two differential outputs at 80 GHz, a programmable divider chain, the charge pump, and all loop filter components. It achieves the lowest W- and D-band phase noise of -93 dBc/Hz at 90 GHz and -87.5 dBc/Hz at 163 GHz, both measured at a 100 kHz offset, and demonstrates an extended locking range of 80-100 GHz at the fundamental frequency, and 160-169 GHz at the second harmonic output of the push-push VCO. The single-ended PLL output power is -3 dBm at 90 GHz and -25 dBm at 164 GHz. The chip consumes 1.25 W from 1.8 V, 2.5 V, and 3.3 V supplies and occupies 1.1 mm × 1.7 mm, including pads.

A Subharmonic Receiver in SiGe Technology for 122$~$GHz Sensor Applications

The iterative design of an integrated subharmonic receiver for 120-127 GHz is presented. The receiver consists of a single-ended low-noise amplifier (LNA), a push-push voltage-controlled oscillator (VCO) with 1/32 divider, a polyphase filter, and a subharmonic mixer. The receiver is fabricated in SiGe:C BiCMOS technology with <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fT</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> of 255 GHz/315 GHz. In the first design the differential down-conversion gain of the receiver is 25 dB at 127 GHz, and the corresponding noise figure (NF) is 11 dB. The 3 dB bandwidth reaches from 125 GHz to 129 GHz. The input 1 dB compression point is at - 40 dBm. The receiver draws 139 mA from a supply voltage of 3.3 V. A subsequent design demonstrates 31 dB differential gain at 122 GHz, and 11 dB NF. The 3 dB bandwidth is from 121 GHz to 124 GHz. The receiver has a NF of 8 dB for 3 GHz IF frequency due to integrated RF bandpass-filtering. It is realized by the lower NF of the LNA, and the LNA itself.