Pulse Width Modulation Scheme Research Articles

Simple Discontinuous Pulse-Width Modulation Scheme for the Loss Reduction of a Dual Inverter Fed an Open-End Winding Induction Motor

This paper presents a simple discontinuous pulse width modulation (DPWM) switching scheme to reduce the switching loss of a single DC-link dual two-level inverter fed an open-end winding (OW) induction motor (IM). The dual inverter system is attractive in many applications due to higher DC-link voltage utilization. Additionally, the OW motor has the potential fault-tolerant capability. However, the use of the dual inverter results in reduced system efficiency due to increased power losses in the inverter. Moreover, an OW motor inherently suffers from a zero-sequence current (ZSC) issue because the open neutral point of the stator windings provides the ZSC path. The ZSC causes negative effects in the system, such as an additional power loss and total harmonic distortion (THD). Thus, this work proposes an optimal DPWM scheme to reduce the inverter loss while suppressing the ZSC. Additionally, this work proposes a strategy to make the average power loss of each inverter equal. The performance of the proposed method is discussed in terms of switching power loss reduction and ZSC suppression. Simulation and experimental results are provided to verify the effectiveness of the proposed DPWM scheme.

Error Calibration of Current Reconstruction Considering Noncentral Sampling for OW-PMSM Drive With Single Current Sensor

In this article, a novel current error calibration scheme considering noncentral sampling is proposed for an open winding permanent magnet synchronous motor (OW-PMSM) drive with a single current sensor. To realize the current reconstruction using a single current sensor, the durations of measurement vectors need to last long enough. Besides, the pulsewidth modulation (PWM) of the dual inverters is complicated, where the switching signals of two inverters need to be calculated simultaneously. Hence, the modified PWM strategy is developed to simplify the PWM procedure and extend the duration of measurement vectors. Nevertheless, the sampling error exists, because the bus current samplings take place sequentially at the measurement vectors instead of simultaneously at the central point. This will lead to a significant error in the reconstructed current, degrading the operation performance. Therefore, an online current calibration scheme is proposed to compensate for the current sampling error, which requires neither observer nor offline measurement to obtain the back electromotive force (back EMF). With the proposed calibration strategy, the precision of the reconstructed current can be significantly improved. Experiments are performed on an OW-PMSM drive to verify the effectiveness of the proposed strategy.

A Single-Phase Common-Ground Five-Level Transformerless Inverter With Low Component Count for PV Applications

Multilevel inverters (MLIs) featuring reactive power ability and common ground (CG) have become much popular in transformerless grid-tied photovoltaic applications. A switched-capacitor (SC) based five-level transformerless inverter configuration is thus proposed in this article, which requires only six switches, one diode, three capacitors, and one input dc voltage supply. Notably, only four power switches are operated in high frequency, thus, the switching losses are reduced. Moreover, the presented topology can effectively tackle the leakage current problem using a CG architecture. A multicarrier phase disposition pulsewidth modulation strategy is employed to achieve reactive power regulation and SC voltage self-balancing. To achieve the neutral point voltage balance of the presented five-level inverter, a simple closed-loop voltage-balancing control method is proposed. The operation principles with modulation strategy and voltage self-balancing of SC are discussed in depth. Comparisons between the proposed and the state-of-the-art MLIs are presented in detail. Finally, experimental tests on a single-phase 1.1-kW prototype validate the appropriate performance of the proposed inverter.

An alternate hybrid PWM for uniform thermal sharing in single phase voltage-source inverter

The most prevalent reason for IGBT failure in voltage-source inverter (VSI) is thermal stress, which is influenced by the topology and modulation technique adopted. Hence, it is crucial to understand the impact of common sinusoidal pulse width modulation (PWM) strategies on the thermal behavior of VSI and develop improved PWM techniques. This paper presents an alternate hybrid PWM (AHPWM) switching sequence for a single-phase VSI to decrease its thermal stress and prolong its lifetime. To evaluate the number of cycles to failure of VSI, power loss and thermal analysis were conducted for VSI with AHPWM and compared with conventional PWMs. The thermal cycles experienced by IGBTs with different modulation techniques were experimentally validated using a laboratory prototype of VSI. These findings suggest that by employing AHPWM, the likelihood of VSI failure is reduced by at least one-and-a-half times, resulting in lower VSI maintenance costs.

Improved Operation of the Step-Up Converter with Large Voltage Gain and Low Voltage on Capacitors

This work proposes an improvement for a recently proposed converter. The discussed converter is the so-called low-voltage in capacitors (LVC). It offers a larger voltage gain compared to the standard step-up or boost converter while operating with a relatively low voltage in their capacitors (lower than the voltage at the output port). The improvement consists of a modification in the pulse width modulation (PWM) scheme. The new modulation scheme allows for a reduction in the voltage ripple at the output port, which means an improvement in the power quality. The LVC converter contains two transistors, but it was proposed to operate with a single switching signal. The new PWM scheme is based on two switching signals with the same duty cycle (same waveform and same average time in high) but 180° of phase shift among them. The PWM scheme significantly affects the voltage ripple at the converter’s output port. The voltage ripple reduction at the converter’s output port is achieved without increasing the transistor switching frequency and without modifying the circuit parameters (capacitance in capacitors or inductance in inductors). The article starts by introducing the converter. Then, it presents its mathematical model, including the calculation of the voltage ripple at its output port. The experimental results performed on the LCV in both the former and the proposed operation prove the reduction in the voltage ripple, and the comparison also includes the traditional boost converter.

Trapezoidal reference-based single carrier pulse width modulation method for multilevel converters with novel FPGA implementation

Recent attention has focused on trapezoidal reference-based pulse width modulation (PWM) schemes in multilevel converters (MLCs) with easier implementation and better harmonic performance. Nevertheless, these studies utilize trapezoidal reference only for multi carrier PWM methods and details of FPGA implementation are not provided. This paper proposes a trapezoidal reference-based single carrier PWM (TSC-PWM) with its novel FPGA implementation. Design parameters of TSC-PWM is determined such that harmonic performance is maximized and architectural details of FPGA implementation of TSC-PWM are provided. Results reveal that TSC-PWM significantly reduces the resource utilization compared to other methods. Single-phase three-module cascaded H-bridge MLC (CHB-MLC) is established in both simulation and experimental platforms. Results indicate that the TSC-PWM provides better harmonic performance along with higher DC utilization ratio compared to other methods. Moreover, both half-wave and quarter-wave symmetries are ensured with TSC-PWM.

An Enhanced Space Vector PWM Strategies for Three Phase Asymmetric Multilevel Inverter

This work presents the two space vector pulse width modulation (SVPWM-I and SVPWM-II) strategies for eleven-level (11L) asymmetric cascaded H-bridge (CHB) multilevel inverter (MLI). Depending on the isolated structure and nonappearance of capacitor voltage balancing issues, the CHB MLI structure is favoured. These days, the SVPWM control method is accomplished superior consideration among the diverse PWM methods. In common, the SVPWM strategy is realized based on deteriorating higher-level hexagons into a lower level hexagon (2-level). Compared to the classical SVPWM strategy, the proposed SVPWM-I strategy decreases the memory and mathematical burden necessity included within the demonstration of eleven-level SVPWM devoid of losing the inverter output voltage (AC) contour by diminution the number of two-level hexagons. Also, the SVPWM-II strategy is presented, which incredibly diminishes the mathematical endeavours. The presented two SVPWM methods performed on an eleven-level asymmetric CHB multilevel inverter (MLI) by utilizing SIMULINK/MATLAB program tool and are compared with conventional sinusoidal PWM and Third harmonic injection (THI) PWM methods to confirm the proposed SVPWM methods. The proposed SVPWM methods give higher AC RMS voltage and lower harmonic distortion when compared to SPWM and THIPWM methods. To validate the presented two SVPWM control schemes, hardware results are taken on asymmetric eleven-level CHB MLI.

An assessment of advanced DC-link based reversing voltage type multilevel inverter topologies

AbstractIn this paper, advanced DC-Link (DCL) based reversing voltage type Multilevel Inverter (MLI) topologies by compensating the difficulties in the conventional MLIs are reviewed. These topologies consist of less switching components and driver circuits when compared with conventional MLIs predominantly in higher levels. Consequently, installation area, total cost and hardware difficulties are reduced by increasing the voltage levels. The unipolar based Pulse Width Modulation Schemes (PWMS) will improve DCL inverters performance. This paper presents unipolar Multi-Reference (MR) based sine and space vector PWMS with single triangular carrier wave for generating required levels in output voltage. Comparison between UMR sine and space vector PWMS for DCL inverter topologies is presented in terms of Fundamental Output Voltage (FOV) and Total Harmonic Distortion (THD). The research tries to establish the survey analysis for single-phase 7-level DCL based reversing voltage type MLI topologies with UMR based sine and space vector PWMs. Finally, to confirm the feasibility of proposed DCL-MLIs in terms of FOV and THD the simulation results are incorporated. Further, the prototype model is developed for single-phase 7-level DCL inverter with Field Programmable Gate Array (FPGA) based UMR sine and space vector PWMS to authenticate simulation results. The efficiency of the proposed cascaded MLI achieves the value of 99.003%.

Modified RPWM Strategy Based on Level-Shifted Random Carrier and Power Balance to Reduce the PWM Voltage Noise in Three-Phase CHB Inverters

Aimed at the pulse width modulation (PWM) voltage noise and power imbalance in three-phase cascaded H-Bridge (CHB) inverters, a modified random PWM (RPWM) strategy, named the power-balanced RPWM (PB-RPWM) strategy, is proposed in this paper. The PB-RPWM strategy mainly includes three steps: (1) random pulse signals are generated by compared modulation wave with level-shifted random carriers; (2) the random pulse signals are circularly distributed between CHB units by a logic operation method, and then the driving pulse signals of switching devices are produced; (3) the driving pulse signals are used to control the inverter. Under the PB-RPWM strategy, the spectra of the line voltage become uniform and continuous, that is, the PWM voltage noise of the line voltage can be effectively reduced. The output voltage of a single H-bridge unit can contain three basic voltages within 3/2 TA, that is, the power balance between CHB units can be realized. When compared with conventional non-random and random PWM strategies, the PB-RPWM strategy has a lower PWM voltage noise and smaller total harmonic distortion (THD). When compared with the level-shifted PWM (LS-PWM) strategy, the PB-RPWM strategy has a balanced power performance. The effectiveness and feasibility of the PB-RPWM strategy is verified by abundant simulations and experiments.

Current Sharing Strategy of Three-Phase Series Capacitor Buck Converter for Wide Output Voltage Range Application

Series capacitor buck (SC Buck) converters are widely used in voltage regulator modules (VRMs), electric vehicle, photovoltaic (PV) systems, and so on, for the reason that these converters have the characteristics of high step-down ratio and large output current. However, these characteristics can be realized only when the converter operates in a limited duty-cycle range. In this article, a modified pulsewidth modulation (PWM) scheme based on the principle of ampere-second balance is proposed for the three-phase SC Buck converter to solve the problem. The ampere-second balance of series capacitors is used to balance the phase currents over the entire duty-cycle range. The operating modes, voltage gain and current sharing performance of the converter, control diagram of the proposed converter, and parameter variation analysis are given. Theoretical analysis shows that with the proposed PWM scheme, the converter will have a larger output voltage, unified linear voltage gain expression, and sensorless automatic current sharing over the full duty-cycle range. Moreover, the results show that the parameter variation has nearly influence on the current sharing effect and the excellent balanced current can be achieved under steady state and transient state using the proposed PWM scheme. Finally, a 100-W experimental prototype has been fabricated to verify the performance of the proposed PWM scheme.

SVPWM Strategy Based on the 45$^\circ$ Coordinates to Suppress Common-Mode Voltage for Multilevel Converters

This article proposes an optimized space vector pulsewidth modulation (SVPWM) strategy with minimum common-mode voltage (CMV). Compared with earlier SVPWM methods, the proposed optimized strategy is implemented in the 45 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^\circ$</tex-math></inline-formula> coordinates. Locating the sector triangle, calculating the duty cycles, and determining the switching sequences require only basic arithmetic operations, which greatly reduces the computational complexity. The switching state with minimum CMV corresponding to the space vector can be calculated directly. The proposed optimized modulation strategy effectively solves the problem that the traditional SVPWM is difficult to be implemented as the number of levels increases. It can be easily extended to any level converters without additional computational burden. Based on the proposed optimized SVPWM strategy with minimum CMV, the SVPWM strategy for eliminating CMV is proposed. The proposed SVPWM strategy for eliminating CMV improves the utilization of the redundant cells and reduces the total harmonic distortion of phase voltages without increasing the difficulty of implementing the SVPWM algorithm. Finally, the proposed two SVPWM strategies are verified with extensive simulations and experiments.

Optimized Carrier-Based DPWM Strategy Adopting Self-Adjusted Redundant Clamping Modes for Vienna Rectifiers With Unbalanced DC Links

When the Vienna rectifier operates at unbalanced dc links, the conventional carried-based discontinuous pulsewidth modulation (CB-DPWM) strategy suffers from the neutral point (NP) voltage fluctuation and the input current distortion. An optimized CB-DPWM strategy adopting self-adjusted redundant clamping modes is proposed in this article to solve the above issues. To reduce the input current distortion under unbalanced dc links, the modulation waves of CB-DPWM are modified according to the subsector redivision, and the limited operation region can be obtained. To extend the operation range of the Vienna rectifier, the voltage vector trajectory of CB-DPWM is optimized combined with the current error minimization and the voltage loss area compensation. To minimize the NP voltage fluctuation, the redundant clamping modes under unbalanced dc links are self-adjusted in real time according to the unbalanced degree. Moreover, the NP voltage fluctuation of the proposed strategy is evaluated by the root mean square of the NP current fluctuation. The effectiveness of the proposed strategy is verified by experiments on a Vienna rectifier platform.

A Three-Phase Dual-Output T-Type Three-Level Converter

A novel three-phase dual-output T-type three-level converter (DO-T-TLC) topology is proposed in this article. The proposed topology has the dc-link and two sets of three-phase ac voltage output terminals. The topology of DO-T-TLC is introduced. Then, the operating principle of multiplexing switches and the available switching states of converter are analyzed, including current path, output phase voltage level, and blocking voltage of different switching states. The phase disposition pulsewidth modulation scheme with dc offsets is discussed in detail, and the key problems of the modulation scheme under both the common frequency and different frequency operation modes, such as voltage level selection, displacement angle constraint, and modulation index range, are studied. For the imbalance of two series capacitors in the dc-link, the mechanism is first revealed, and then a dc-link capacitor voltage balance method to control the average neutral point current is proposed. When DO-T-TLC is used in different operation modes, the ability and effect of this method to balance capacitor voltages are summarized. A low-power three-phase prototype is built, and the experimental results are given to verify the feasibility of the proposed topology and the effectiveness of the modulation scheme to control the voltage balance.

A New Topology and Modulation Strategy to Suppress the Leakage Current in Transformerless Cascaded H-Bridge Inverters in PV Application

The use of transformerless inverters is common due to the lower cost, lighter weight, and higher efficiency. The lack of the transformer leads to the leakage current circulation through the parasitic capacitors, which increases the power losses, electromagnetic interferences, and safety issues. In this article, first, the proposed cascaded H-bridge (CHB) -based inverter’s equivalent common-mode (CM) model is determined. Then, a new multicarrier pulsewidth modulation strategy is proposed to suppress the leakage current. In the presented method, new redundancy states are provided due to the use of just one blocking switch. These extra redundancy states and the proposed modulation strategy help to keep the CM voltage (CMV) constant and suppress the leakage current. The validity of the proposed solution is verified by simulation in the MATLAB/Simulink environment. In addition, a universal prototype with a power rating of 600 W is built and tested, and the experimental results are presented to confirm the theoretical and simulation results. The experimental results show a maximum efficiency of 98.5% and a European efficiency of 98.3%. The proposed topology is also compared to the existing transformerless topologies to show its effectiveness.

A Linear-Resonant Hybrid Bridge DC–DC Converter

A linear-resonant hybrid bridge dc–dc converter is proposed in this article. The converter adds a set of linear-bridge-arm based on the traditional half-bridge <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LLC</i> resonant converter. This converter can operate in a high-voltage-gain (HG) mode and a low-voltage-gain (LG) mode by adopting pulsewidth modulation strategy and pulse frequency modulation strategy respectively. In the HG mode, it can control the inductor current increasing linearly by the linear-bridge-arm to obtain higher voltage gain and wider output range than the traditional <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LLC</i> resonant converter, and the voltage gain is less affected by the magnetizing inductor. In the LG mode, the voltage gain characteristics of the proposed converter are similar to that of the traditional <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LLC</i> resonant converter. The proposed converter works with negligible feedback current. In addition, all power switches can realize soft-switching in a wide load range. The working principle, voltage gain, design approach, and topologies comparison are introduced in this article. Finally, an experimental prototype based on constant current and constant voltage charging was built, with 400 V input voltage, 180–310 V output voltage, and 0–4.5 A output current. The experimental results verified its feasibility.

A Simplified DTC-SVPWM Scheme for Induction Motor Drives Using a Single PI Controller

Apart from variable switching frequency, a major issue in direct torque controlled (DTC) induction motor drives is the high torque ripple, which can be minimized by incorporating suitable pulsewidth modulation schemes such as space vector pulsewidth modulation (DTC-SVPWM) and duty ratio control DTC. However, the simplicity and robustness of the DTC scheme are compromised due to the high computational complexity and requirement of a number of motor parameters for the control. In this article, a simple and elegant control algorithm for the realisation of the DTC-SVPWM that is less dependent on motor parameters is proposed. The stator flux-linkage space vector angle needed to generate the reference torque for the DTC operation is computed based on the basic torque equation and the reference stator phase voltage needed for the SVPWM is determined in turn in every sampling period. For the modulation, a carrier-based space vector pulsewidth modulation (CSVPWM) scheme is adopted to get low torque ripple at constant switching frequency. The proposed speed control scheme avoids the use of rotor parameters and rotating reference frame transformations. It requires no sector identification and only one PI controller is needed for the speed control. Though the scheme has comparable torque ripple as that of the conventional DTC-SVPWM scheme, it significantly reduces the computational burden. Hardware results on a three-phase, 2 HP, 415 V induction motor are presented to validate the performance of the proposed control scheme.

An Optimized Carrier Phase-Shifted Modulation Strategy for Cuk PV Inverter

There exists the problems of output voltage zero-point drift and high even harmonic content of the three-phase Cuk liftable voltage photovoltaic (PV) inverter when it adopts the conventional carrier modulation method. In view of these, a new optimized Phase-Shifted Pulse Width Modulation (PSPWM) strategy is proposed. Firstly, the optimal zero-sequence component is determined based on the inverter topology and control objectives. Next, the zero-sequence component is injected into the sinusoidal signal and used as the new modulating signal so that the carrier pulse width modulation is equivalent to the space vector pulse width modulation. Finally, the carrier and modulating waveforms are blended in a superior manner, and a new logical operation is applied to generate the required switching drive signals for the control of the inverter switching tubes. In order to verify the effectiveness of the strategy, simulation and experimental platforms were constructed, and numerous simulations and experiments were done. The results show that the modulation strategy can solve the output voltage zero drift problem effectively, and suppress the even harmonics effectively, meanwhile, the harmonics are mainly concentrated near the primary frequency, which significantly reduces the total harmonic content and greatly improves the output voltage waveform. In addition, the modulation can be achieved by reducing one carrier signal, thus simplifying the modulation process and the design of the digital signal system.

A Sensor-less Surface Mounted PMSM for Electronic Speed Control in Multilevel Inverter

Recent advancements in power electronics technology evolves inverter fed electric motors. Speed signals and rotor position are essential for controlling an electric motor accurately. In this paper, the sensorless speed control of surface-mounted permanent magnet synchronous motor (SPMSM) has been attempted. SPMSM wants a digital inverter for its precise working. Hence, this study incorporates fifteen level inverter to the SPMSM. A sliding mode observer (SMO) based sensorless speed control scheme is projected to determine rotor spot and speed of the multilevel inverter (MLI) fed SPMSM. MLI has been operated using a multi carrier pulse width modulation (MCPWM) strategy for generation of fifteen level voltages. The simulation works are executed with MATLAB/SIMULINK software. The steadiness and the heftiness of the projected model have been investigated under no loaded and loaded situations of SPMSM. Furthermore, the projected method can be adapted for electric vehicles.

A novel hybrid discontinuous PWM algorithm for 3L-NPC inverter

Wider linear modulation range, less switching loss and simplicity are the goals pursued by various modulation methods of multilevel inverters. This paper proposes a new hybrid discontinuous pulse width modulation (HDPWM) strategy for 3L-NPC inverter that can achieve the above goals to a certain extent. According to the position of the reference voltage vector and the actual situation of the neutral point voltage, different control modes and clamping types are selected. The neutral point voltage is controlled by DPWM strategy, which cannot only greatly reduce the switch loss, but also maintain the balance of the neutral point voltage and expand the linear modulation range. The implementation of the algorithm combines the advantages of carrier-based PWM (CBPWM) and space vector PWM (SVPWM). There is no need to select the nearest three vectors (NTV) and calculate their dwell time. Only the reference voltage needs to be modified according to the control requirements, and then by comparing the modified reference voltage with the carrier, the driver pulse required by the switching devices can be generated. Compared with the existing PWM methods, it is more simple and easy to implement. Experimental results verify the validity of the method.

Three-Phase Hybrid Converter With Simultaneous DC and AC Outputs

A novel topology of three-phase hybrid converter (TP-HC) which can supply simultaneously both DC and AC loads is presented. This topology is obtained by adding three switches to T-type three-level inverter. Consequently, this converter can achieve one group of DC/DC power transformation and another three-phase three-level AC voltage outputs with adjustable amplitude. The topology and operation modes of the proposed hybrid converter are introduced. Then the working principle and the available switching states of converter are analyzed, including current path, output phase voltage level and blocking voltage of different switching states. The characteristics of three typical hybrid converters are compared. A strategy combining time-sharing modulation and virtual space vector modulation (VSVPWM) is adopted to realize simultaneous DC and AC outputs of the converter. Then the capacitance voltage balance of the DC link is realized. In order to simplify the modulation strategy, a carrier based on pulse width modulation (CBPWM)strategy is proposed. Then, boost ratio of this converter is analyzed in detail. Finally, the feasibility of the proposed topology and the effectiveness of modulation strategy are verified by simulation and experiment.