Pulse Width Modulation Pattern Research Articles

Three 1-bit speckle-embedded pulse-width modulation patterns for robust absolute 3D measurement

In three-dimensional (3D) shape measurement techniques using structured light, 1-bit pulse-width modulation (PWM) patterns and 1-bit speckle patterns can be projected at high speed. However, when combining PWM and speckle patterns to integrate their advantages, the decoupling problem is insurmountable. In this work, a novel 1-bit speckle-embedded PWM (SPPWM) method was proposed to achieve absolute 3D shape measurement using only three binary patterns. Our method consists of three main steps: First, a sinusoidal pattern reconstruction network was proposed to eliminate the high-order harmonics and speckle patterns in the SPPWM patterns and obtain high-quality sinusoidal patterns. Second, a multi-temporal spatial correlation matching algorithm was proposed to obtain a coarse disparity map from the three SPPWM patterns. Third, the high-accuracy wrapped phase map is used as an additional constraint for refining the coarse disparity map to obtain the final high-accuracy disparity map for absolute 3D measurement without phase unwrapping. Our method combines the advantages of fringe projection profilometry techniques for high-precision wrapped phase retrieval and speckle correlation matching algorithms for robust and unambiguous disparity map calculation. The experimental results demonstrated that our method could realize high-precision absolute 3D shape measurement with an accuracy of 0.057 mm using only three 1-bit SPPWM patterns. Furthermore, different simulation noises were used to demonstrate the robustness of the proposed method.

Matrix-Based Approach for Open-Circuit Fault-Tolerant Analysis and PWM Design of Active Neutral-Point-Clamped Converters

Active neutral-point-clamped converter adds open-circuit fault-tolerant (OCFT) capability compared with the widely used original neutral-point-clamped (NPC) topology. However, such capability is hard to utilize due to difficulties in pulse-width modulation (PWM) design and the randomness of failure points, particularly in high-level converters. Current research mainly focused on low-level topologies with a limited number of fault scenarios; moreover, the analysis and design are performed in a nonsystematic way. In this article, the OCFT operations of active NPC (ANPC) converters with multiple fault switches are investigated and the systematic PWM design process is proposed. First, different matrices are proposed for the ANPC converters to capture the complicated topology information and achieve an exhaustive analysis of the topological redundancy. Then, a step-by-step process is proposed to derive the suitable OCFT PWM patterns. The five-level ANPC converter is investigated as an example. Its experimental results validate that the proposed approach can 1) properly predict the behavior of converters systematically so that the tolerable faults and intolerable can be identified during the design procedure, and 2) the inherent fault-tolerant capability of the five-level ANPC converter can be guaranteed through the proposed method, and 3) multiswitch open-circuit faults can be easily dealt with by implementing suitable carrier-based PWM schemes.

A Generalized Phase-Shift PWM Extension for Improved Natural and Active Balancing of Flying Capacitor Multilevel Inverters

The emergence of wide bandgap power devices has brought the attention back to the flying capacitor (FC) multilevel inverters with a large number of stages, in an effort to increase the power density by minimizing the passive components. The main challenge that such systems face, particularly the ones based on high-frequency Gallium-Nitride devices and small-value ceramic capacitors, relate to the stringent requirements for precise and fast capacitor balancing. Conventional <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">natural balancing</i> techniques exhibit poor settling times, while most improved natural balancing methods are not easily scalable to more than five levels. The alternative of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">active balancing</i> normally requires one isolated sensor per FC which increases the overall system cost and footprint, or a single ac-side sensor that is more compact but calls for sophisticated PWMs that again are not available for multiple levels. In this paper we introduce a generalized pulse width modulation (PWM) strategy based on the phase-shift and carrier swapping principles for an arbitrary number of levels. We provide an easy and intuitive method for the extraction of the PWM pattern, the switching states, and their sequence. Simulations were carried out in Matlab/Simulink and experimental tests were conducted on a single-phase 7-level GaN inverter prototype. Not only is the extended PWM advantageous in natural balancing, but it also provides the right zero switching states for ac-side FC sensing in active balancing.

Safety Operation Area of Zero-Crossing Detection-Based Sensorless High-Speed BLDC Motor Drives

In the high-speed brushless dc drives, long commutation freewheeling duration will increase the difficulty of sensorless operation that is based on the back electromotive force (EMF) zero-crossing detection. In extreme cases when the freewheeling angle exceeds 30°, the zero crossing of back EMF will be undetectable, resulting in the failure of sensorless drives. As a result, the sensorless safety operation area (SOA) is limited by the long freewheeling angle issue. In this article, it is found that the pulsewidth modulation (PWM) patterns have a big influence on the freewheeling angle. Hence, in the first place, through analytical methods, the mechanism that how different PWM techniques affect the freewheeling angle is investigated. The PWM pattern resulting in a minimum freewheeling angle is identified. Furthermore, a method to predict the SOA is developed, which provides a theoretical way to verify whether the predesigned torque and speed area can be achieved with the given motor parameters. Finally, the theoretical analysis is verified by the simulation and experimental results.

A Modular Design Approach to Provide Exhaustive Carrier-Based PWM Patterns for Multilevel ANPC Converters

The number of applicable carrier-based pulsewidth modulation (PWM) patterns increases with the growth of output levels in scalable multilevel topologies, such as active-neutral-point-clamped (ANPC) converters. Therefore, it is hard to optimize PWM for such topology, especially with large output levels. In this paper, a simplified and modular carrier-based PWM design approach for multilevel ANPC converters is proposed. Inspired by the decomposition theory, the topology decomposition is introduced in this paper to decompose an N -level ANPC converter into low-level subtopologies. Then, the complete set of applicable PWM patterns is derived based on ANPC operation principles, which makes it possible to optimize the performance based on the various requirements in applications. Meanwhile, the carrier-based PWM is implemented through the utilization of subtopologies with low-level modulation schemes, such that the design process of carrier-based PWM is greatly simplified and modularly realized. Both the complete PWM patterns and PWM design examples with experimental results of several ANPC converters are provided to show the feasibility and modularity of the proposed method.

Fault‐tolerant control of DSBLDC motor drive under open‐circuit faults

Doubly salient brushless dc (DSBLDC) motor drive system has attracted increasing attention due to the rugged rotor structure, brushless operation and low cost. The switch open-circuit (OC) fault increases the torque ripple and decreases the maximal output power of DSBLDC motor drive system. A fault-tolerance control strategy for switch OC circuit is proposed in this study. The back electromotive force (BEMF) current would occur in a pulse-width modulation (PWM) pattern. It severely degrades the proposed method's fault-tolerant performance. So the cause of the BEMF current is analysed and BEMF current is suppressed by specific PWM pattern. Finally, the fault-tolerance control strategy is verified by experiment results and the selection PWM pattern is proved to be correct and practical.

Integral‐series Fourier analysis of chaotic PWM patterns for common mode voltage stresses

In this study, the theory of pulse width modulation (PWM) is developed for both sine-wave PWM (SPWM) and chaotic sine-wave PWM (CSPWM). In SPWM, power spectra are analysed by an analytical method such as double Fourier series (DFS) technique, and the integral-series Fourier method is fully devised and analytically theorised for CSPWM. It is shown that the root-mean-square value of inverter's zero-sequence voltage does not rely on carrier and reference frequency in fixed-frequency SPWM, while in CSPWM, this depends on frequency modulating gain and chaotic sequence of numbers. Also, the computation time of purely numerical harmonic analysis can be much heavier than analytical ones. Furthermore, the DFS and integral-series Fourier methods are applied to SPWM and CSPWM with two different frame sizes of squirrel cage motors for the shaft voltage and the electro-magnetic interference (EMI). The numerical and experimental results show that CSPWM can have positive effect on the shaft voltage while it definitely weakens the EMI problems.

An Efficient Four-State Zero Common-Mode Voltage PWM Scheme With Reduced Current Distortion for a Three-Level Inverter

In this paper, a new carrier-based pulse width modulation (PWM) strategy providing common-mode voltage (CMV) elimination and reduced current ripple in a three-level neutral-point-clamped inverter is introduced. The employed switching sequences are made up of the three zero CMV (ZCMV) vectors, and one among the three vec-tors is applied at two ends of a half-carrier cycle. The output current ripple characteristics pertaining to those switching sequences are investigated. In a carrier cycle, the root-mean-square current ripple minimization is analyzed and an optimal sequence is derived accordingly. The presented PWM scheme results in a considerably reduced current harmonic distortion in a wide modulation region as compared to the two existing ZCMV schemes on the same average switching frequency. Also, an implementation of sawtooth-carrier-based PWM patterns is proposed for further improvement of the harmonic performance. The algorithm requires small computational burden and is straightforward for an online implementation. Simulation and experimental results are both provided to validate the good performance of the proposed PWM method.

Hybrid Synchronized PWM Schemes for Closed-Loop Current Control of High-Power Motor Drives

For high-power drives, switching frequency is usually restricted to several hundred hertz to minimize the switching losses. To maintain the current distortions and torque ripples at a reasonable level, synchronized pulse patterns with half-wave and quarter-wave symmetries are employed. The analytic compensation is derived by Fourier analysis to ensure the proportionality between the voltage reference and the output voltage of an inverter for pulse width modulation (PWM) with low pulse ratio. A simple yet very effective method with varying sampling rate is proposed to maintain synchronization even for fast dynamic processes. The fast and smooth transition between different PWM patterns is achieved by compensating phase angle of the voltage reference through the analysis of stator flux trajectories. The effectiveness of the proposed method is validated on a down-scaled 2.2-kW induction motor drives.

Subfundamental Cycle Switching Frequency Variation for Switching Losses Reduction of a Two-Level Inverter Traction Drive

This paper proposes a method to vary the switching frequency within a fundamental cycle to reduce the switching losses of a two-level inverter while maintaining the peak–peak current ripple within a predefined limit. Unlike conventional strategies, the proposed technique utilizes precomputed switching frequency variation factors without relying on prediction or optimization techniques, since the peak–peak current ripple follows a definite trajectory within a fundamental cycle. Moreover, the variation in switching frequency is further controlled based on the operating carrier ratio and modulation index. The proposed strategy has been validated through both the simulation and experimental results on a permanent magnet synchronous motor drive for the space vector and discontinuous pulsewidth modulation patterns, and the results demonstrate that it reduces the two-level inverter switching losses up to 15%.

A Three-Phase Multioptimal PWM Implemented on 2-Gbit Flash Memory Integrated Circuits

This paper further develops the concept of very large size flash-memory-based pulsewidth-modulated (PWM) algorithms for three-phase inverters. Such algorithms differ from the conventional counter-based implementation, and they follow a preprogrammed optimal PWM pattern that is read from a very large size memory with magnitude and phase as coordinates. Any sequence of states is thus possible within a PWM sampling interval. A novel digital structure has been built around the newly released flash memory integrated circuits. The paper demonstrates the feasibility of operation at any PWM sampling frequency up to 20 kHz when using gigabit-size flash memory integrated circuits along any low-cost microcontroller with an SPI peripheral. To empower the concept, a multioptimal PWM has been proposed and implemented on a 2-Gbit memory table. The harmonics of the phase currents are reduced by more than 40% while a constant PWM sampling frequency is maintained in order to comply with the conventional vector control methods for grid or motor applications.

A Preprocessed PWM Scheme for Three-Limb Core Coupled Inductor Inverters

A discontinuous pulse-width modulation (PWM) scheme is presented for a six-switch three-limb coupled inductor inverter. Three-level PWM phase output voltages are produced with a reduced switch count and reduced dv/dt stresses on loads and output filters. The PWM scheme described lowers the coupled inductor and semiconductor losses by lowering the inductor winding high-frequency current ripple using two techniques: 1) winding excitation flipping within each carrier cycle; and 2) the inductor magnetic flux is kept within the three-limb core, neglecting natural leakage, by avoiding switching states that produce common-mode voltage excitation of the three-limb inductor. To make best use of the nonstandard switching patterns produced, reference signals are preprocessed before being delivered to the PWM modules using only one carrier signal: representing an approach well suited for implementation in a low-cost digital signal processor. The digital output signals of each PWM module represent the desired switching states of each switch in the inverter. This approach contrasts with previous published work, where postprocessing of the PWM module output signals is necessary using digital logic circuitry, such as a field-programmable gate array. Experimental results, with inductor loss and inverter efficiency comparisons for different operating conditions, confirm that the three-phase six-switch inverter PWM patterns lower the high-frequency current ripple in the inductor windings and, hence, significantly lower the inverter losses and increase the power conversion efficiency.

An Altered PWM Scheme for Single-Mode Seamless Control of AC Traction Motors for Electric Drive Vehicles

In an electric drive vehicle (EDV), the available voltage on a dc-link is limited, and so the inverter output voltage and, consequently, the line motor maximum speed are limited. The fundamental voltage of the inverter output is increased approximately 27% using a square wave (SW) switching pattern instead of a sine wave switching pattern. However, this pattern can only be used at high speeds, and at lower speeds a pulsewidth modulation (PWM) pattern should be used. In order to achieve proper control, the switching pattern should be changed seamlessly. In the present paper, a new PWM scheme for single-mode seamless control of Vernier motors is proposed. In the proposed scheme, the reference voltage is modified to change the switching pattern continuously so that the voltage changes smoothly from a high-frequency pattern to an SW and voltage discontinuity does not occur. Experimental results reveal that the inverter-switching pattern changes smoothly from a sinusoidal PWM pattern to an SW pattern, and so seamless control from the constant-torque region to the constant-power region, and vice versa, is achieved. Since the proposed scheme is a single-mode control, it is much simpler than current technologies, which are based on multimode controllers. Also the proposed method has a lower total harmonic disturbance (THD) as well as a lower harmonic distortion factor (HDF) compared to some existing methods.

An SD Card Flash-Memory-Based Implementation of a Multioptimal Three-Phase PWM Generator

This paper demonstrates for the first time the use of a very large secure digital card flash memory to the design of a three-phase pulse width modulation (PWM) generator and describes the hardware and software used for implementation. The new digital architecture differs from the conventional counter-based implementation, and it follows a preprogrammed optimal PWM pattern that is read from memory with magnitude and phase as coordinates. This architecture allows the inclusion of multiple optimization criteria within the PWM pattern. This digital architecture becomes valuable since the switching instants can be set in any conceivable manner, away from the rigid constraint of a repetitive sequence of states on each PWM period. Experimental results validate that the proposed new architecture allows simple and low cost implementation of complicated PWM patterns with harmonic reductions that could not otherwise be achieved for low cost.

A Reduced Switching Loss PWM Strategy to Eliminate Common-Mode Voltage in Multilevel Inverters

This paper introduces a novel pulse width modulation (PWM) technique to eliminate common-mode voltage in odd-multilevel inverters using the three zero common-mode vectors principles. Similarly, as in conventional PWM for multilevel inverters, this PWM can be properly depicted in an active two-level voltage inverter. With the help of two standardized PWM patterns, the characteristics of the PWM process can be fully explored in that active inverter as a switching time diagram and switching state sequence. Due to an unequal number of commutations of three phases in each sampling period, the switching loss is optimized by a proposed current-based mapping algorithm. The switching loss reduction can be up to 25% compared to the same PWM technique with nonoptimized algorithms. The PWM method has been then generalized as an equipotential PWM control, which is valid to both odd- and even-multilevel inverter s . The theoretical analysis is verified by simulation and experimental results.

Common-Mode Voltage Reduction of Three-Level Four-Leg PWM Converter

This paper presents a carrier-based pulsewidth modulation (PWM) method that reduces the common-mode voltage (CMV) of a three-level four-leg converter. Based on an analysis of space vector PWM (SVPWM) and sinusoidal-PWM switching patterns, the fourth-leg pole voltage of a three-phase converter, known as the “f pole voltage,” is manipulated to reduce the CMV. To synthesize the f pole voltage for the suppression of the CMV, positive and negative pole voltage references of the f leg are calculated. In addition, the offset voltage to prevent distortion of the a, b, and c phase voltages regarding the neutral point is deduced. The proposed PWM strategy can be easily implemented in the software of a DSP-based converter control. The three-level four-leg converter with the proposed PWM algorithm results in a remarkable reduction in the peak-to-peak value of the CMV. From the simulation and the experimental results, the peak-to-peak value of the CMV when using the proposed PWM method is 33% compared to that when using the SVPWM method, while the number of CMV transitions during the switching period in the proposed PWM method is only 25% of that when using the SVPWM method.

Dual-Output Single-Stage Bridgeless SEPIC with Power Factor Correction

This study proposes a dual-output single-stage bridgeless single-ended primary-inductor converter (DOSSBS) that can completely remove the front-end full-bridge alternating current-direct current rectifier to accomplish power factor correction for universal line input. Without the need for bridge diodes, the proposed converter has the advantages of low component count and simple structure, and can thus significantly reduce power loss. DOSSBS has two uncommon output ports to provide different voltage levels to loads, instead of using two separate power factor correctors or multi-stage configurations in a single stage. Therefore, this proposed converter is cost-effective and compact. A magnetically coupled inductor is introduced in DOSSBS to replace two separate inductors to decrease volume and cost. Energy stored in the leakage inductance of the coupled inductor can be completely recycled. In each line cycle, the two active switches in DOSSBS are operated in either high-frequency pulse-width modulation pattern or low-frequency rectifying mode for switching loss reduction. A prototype for dealing with an <TEX>$85-265V_{rms}$</TEX> universal line is designed, analyzed, and built. Practical measurements demonstrate the feasibility and functionality of the proposed converter.

マトリックスコンバータの高入力力率における出力電圧高調波低減パターンの評価

This paper presents the characteristics of pulse width modulation (PWM) patterns of a matrix converter (MC) under a high input power factor. The various PWM patterns of nine bidirectional switches for the MC can be established. All of the combinations of duty cycles with four commutations in three phases during one control period only using input voltage values under a high input power factor are derived. The PWM patterns of the derived duty cycles for low output voltage harmonics are evaluated. The characteristics and evaluations of the output voltage harmonics and switching losses for the PWM patterns have been verified by theories and experiments.

Novel Pulse-width Modulation Strategy to Minimize the Switching Losses of Z-Source Inverters

This article proposes a novel pulse-width modulation strategy to minimize switching losses of the Z-source inverter. The Z-source inverter has different pulse-width modulation patterns unlike the conventional voltage source inverter. Shoot-through states have been inserted within the zero states of the traditional pulse-width modulation patterns of a voltage source inverter to boost DC input voltage. Thus, the Z-source inverter has six active states, two zero states, and additional shoot-through states differentiating the Z-source and conventional voltage source inverters. The currents flowing through the switches of the Z-source inverter are larger than those of the conventional voltage source inverter, because Z-network currents must flow through the switches during the shoot-through states. Therefore, shoot-through currents increase the total switching losses of the Z-source inverter. In this article, switching losses of the Z-source inverter with the existing pulse-width modulation strategy are analyzed in detail. Then, new modulation signals of the Z-source inverter are introduced to produce unique pulse-width modulation patterns that minimize the switching losses of the Z-source inverter. The switching losses of the Z-source inverter with both pulse-width modulation strategies are simulated and compared. In addition, an experimental system has been built and tested to verify the effectiveness of the proposed strategy.

Three-Phase Multimodule VSIs Using SHE-PWM to Reduce Zero-Sequence Circulating Current

A modular voltage-source inverter (MVSI) uses individual three-phase modules in a shunt connection to allow lower power rated inverters to be implemented in higher power applications. It is standard practice to implement each module with the same pulsewidth-modulation (PWM) pattern. This paper proposes a new PWM approach for MVSIs for which each module is made to operate with a different PWM pattern. It is shown in this paper how more output voltage harmonics can be eliminated with the new approach than with the standard approach and how the new approach can be expanded to significantly reduce zero-sequence current that circulates among the inverter modules. The mathematical formulations needed to generate appropriate PWM patterns for the new PWM approach and experimental results obtained from a prototype MVSI are presented in this paper as well.