Pulse Mode Neural Network Research Articles

Hardware implementation of new bell-shaped pulse mode neural network with on-chip learning and application to image processing

A key task in the hardware implementation of neural networks is the design of activation functions. We focus in this paper on hardware driven simple implementation of a bell-shaped function BSF avoiding complexity and reducing hardware resources with efficient on-chip learning. This implementation is done in pulse mode to take advantage of its valuable features, significantly reducing the hardware cost. The proposed design is flexible and scalable enabling several image processing potential tasks. A first application is devoted to image denoising where a comparison with some existing denoising techniques demonstrates the efficiency of the proposed approach. As a second application, we consider edge detection operation and good approximation features are accordingly obtained. The corresponding design is implemented on a Virtex-II-PRO FPGA platform. Synthesis results prove that the bell-shaped PMNN is not cumbersome, and provides higher performances versus other PMNN architectures in terms of computing speed and required hardware resources.

Edge Detection System using Pulse Mode Neural Network for Image Enhancement

Edge detection of an image reduces significantly the amount of data and filters out information that may be regarded as less irrelevant. Edge detection is efficient in medical imaging. Pulse mode neural networks are becoming an attractive solution for function approximation based on frequency modulation. Early pulse mode implementation suffers from some network constraints due to weight range limitations. To provide the best edge detection, the basic algorithm is modified to have pulse mode operations for effective hardware implementation. In this project a new pulse mode network architecture using floating point operations is used in the activation function. By using floating point number system for synapse weight value representation, any function can be approximated by the network. The proposed pulse mode MNN is used to detect the edges in images forming a heterogeneous data base. It shows good learning capability. In addition, four edge detection techniques have been compared. The coding is written in verilog and the final result have been simulated using Xilinx ISE simulator.

Implementation of a Fingerprint Recognition System Using LBP Descriptor

Abstract Conventional fingerprint recognition systems provide authentication by a direct matching of minutiae points and orientation field. Although several resemblance algorithms have been proposed, reliable automatic fingerprint verification remains a challenge due to the difficulty in alignment for direct matching and the construction of adequate functions for resemblance measurements. In this paper, we propose a solution to the aforementioned problems using a local binary pattern (LBP) descriptor applied to minutiae and orientation fields. The experimental results on the public fingerprint database, Fingerprint Verification Competition (FVC), show high recognition rates. The proposed system was implemented on the platform known as FPGA Virtex-II Xilinix™ (Virtex2p-xc2vp7-FF672) and optimized with respect to hardware resources occupation, based on a co-design methodology. All the proposed algorithms are involved in the design of a mixed software/hardware dedicated system. A classifier based on pulse mode neural networks using floating-point format is proposed.

Hardware implementation of a pulse mode neural network-based edge detection system

In this paper, we exploit the powerful means of neural networks with respect to function approximation. Once they are implemented on-chip, they can be reconfigured for adjusting their input–output relation in order to achieve clustering for decision making but also various image processing tasks such as filtering, edge detection, etc. As an illustration example, we propose here a neural network-based edge detection system. Edge detection reduces significantly the amount of data and filters out information that may be regarded as less irrelevant. It is becoming an important step in segmentation for many image processing applications. The proposed network achieves Canny operator edge detection based on pulse mode operations. Indeed, pulse mode neural networks are becoming an attractive solution in neural network implementation because of the advantages they provide over the continuous mode such as compactness of the pulse multiplier and flexibility of most of the blocs. Such simplicity offers the possibility of on-chip learning. In this work, the proposed edge detection network uses new extended range synapse multipliers operating in a fixed point format with a very simple architecture and adjustable activation functions. To provide the best edge detection, the back-propagation algorithm is modified to have pulse mode operations. Simulation results show the efficient learning and good generalization results. The corresponding design was implemented on a virtex II PRO FPGA platform. Synthesis results prove that the implemented neural network is more compact in terms of size than conventional implementations of a Canny edge detector.

A multilayer neural network with pulse position modulation

AbstractThe problem of the pulse mode neural network is that the synapse weight is bounded between +1 and −1. In order to enhance the weight range, this paper proposes a new weighting method that is a combination of pulse density modulation and pulse position modulation (PPM). The feasibility of the proposed method is verified by experimental MNN with on‐chip learning. A modified back‐propagation algorithm is used for the on‐chip learning. The experimental results show that the proposed MNN architecture has the ability to handle high‐resolution classifying problems and good on‐chip learning capability. © 2003 Wiley Periodicals, Inc. Syst Comp Jpn, 34(13): 36–46, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/scj.10474