Fibre channel (FC) switches are widely used in storage area networks and avionics systems. In this work, the FC protocol, the switching structure and the scheduling algorithm of the FC switch are deeply studied, and a 48-port FC switch is completed on a single-chip field-programmable gate array (FPGA). In addition, an improved scheduling algorithm for Inter-System Link Protocol (iSLP) is proposed for the input and scheduling of optical fiber pulse network data. On this basis, the overall architecture of the FC switch is proposed, the x690tffg1158 FPGA chip is selected, and the FC port control module is designed, which is composed of the receiving controller, the interface state machine, the sending controller, and the flow control. The routing table lookup module of FC switch is designed, the unicast routing table format and multicast routing table format are proposed, and the corresponding unicast and multicast routing table lookup table module architectures are designed. Aiming at the characteristics of high reliability and low distortion in the transmission of high-speed pulse network signals by FC switches, the modulation and demodulation of Bias-T (BIAS-T) are redesigned. The experiment is implemented using Verilog hardware description language (HDL), and Modelsim 10.5 software is adopted to simulate each module of the switch. The switch adopts an 8×N switching structure, which can accurately perform word synchronization. After the link is initialized, the transceivers can send and receive data frames normally. The redesigned BIAS-T is applied to solve the instability of the end of the analog modulation method, and then realize the low distortion and data integrity of the high-speed pulse signal of the FC switch.
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