Pull-down Device Research Articles

A 38.5-fJ 14.4-ns Robust and Efficient Subthreshold-to-Suprathreshold Voltage-Level Shifter Comprising Logic Mismatch-Activated Current Control Circuit

This brief presents a robust and energy-efficient voltage level shifter (VLS) for wide-range conversion from the subthreshold to the suprathreshold regime. The proposed VLS contains a new logic mismatch detection circuit to address the exist contention current of the conversion stage. A power reducer circuit is introduced to increase the drivability of pull-up and pulldown devices in linear and cut-off regions and further energyconsuming improvement. The proposed VLS is simulated using a 0.18-lm process, the minimal convertible voltage is 0.2 V (deep subthreshold region) for the input signal. Post-layout simulation considering process voltage temperature (PVT) variations proves the proposed VLS outperforms previous designs in several aspects. The results report the consuming energy of 38.5 fJ per transition, a static power of 73.4 pW, and a delay of 14.4 ns when converting range is 0.4 V to 1.8 V. The proposed VLS occupies a 59.98-lm2 silicon area.

Modernization of a rolling table before gas cutting machine of bloom CCM

The results of the analysis of the design of the intermediate rolling table in front of the gas cutting machine of the four-strand continuous casting machine (CCM-1) of the electric steelmaking shop of JSC Ural Steel are presented. It is shown that as a result of exposure to high temperatures (due to the unsuccessful location of the gear motor near the high temperature zone), the operability of the gear coupling of the gear motor is often disrupted. To improve the performance of the intermediate rolling table CCM-1, it is proposed to modernise it by installing a pull-down device on each strand directly in front of the gas cutting machine, the working element of which is a drive roller located above the rolling table. Rotation of the roller is carried out from an individual electric drive, and its pressing to the workpiece – by means of a hydraulic drive through a system of levers. This makes it possible to perform all 28 rollers of the rolling table non-drive ones, without changing their location. As a result of the modernization of the intermediate rolling table CML-1 in front of the gas cutting machine, it was possible to simplify its design and reduce the complexity of maintenance and repair by 64 hours per year. Replacing 28 drive rollers with non-drive rollers increases the reliability of their operation, allows you to increase the repair period of operation and thereby reduce the cost of operating costs. In addition, reducing the number of electric motors from 28 to 4 provides significant energy savings. Calculations show that the implementation of design solutions leads to a reduction in the cost of one ton of steel by 0.05 %, an increase in product profitability by 0.19 % and an increase in labor productivity by 0.41 %. Additional capital expenditures of about 1 million rubles are recouped in less than 3 months.

Performance analysis of multi-scaling voltage level shifter for low-power applications

Purpose In complementary metal-oxide-semiconductor (CMOS) logic circuits, there is a direct square proportion of supply voltage on dynamic power. If the supply voltage is high, then more amount of energy will be consumed. Therefore, if a low voltage supply is used, then dynamic power will also be reduced. In a mixed signal circuit, there can be a situation when lower voltage circuitry has to drive large voltage circuitry. In such a case, P-type metal-oxide-semiconductor of high-voltage circuitry may not be switched off completely by applying a low voltage as input. Therefore, there is a need for level shifter where low-voltage and high-voltage circuits are connected. In this paper the multi-scaling voltage level shifter is presented which overcomes the contention problems and suitable for low-power applications. Design/methodology/approach The voltage level shifter circuit is essential for digital and analog circuits in the on-chip integrated circuits. The modified voltage level shifter and reported energy-efficient voltage level shifter have been optimally designed to be functional in all process voltage and temperature corners for VDDH = 5V, VDDL = 2V and the input frequency of 5 MHz. The modified voltage level shifter and reported shifter circuits are implemented using Cadence Virtuoso at 90 nm CMOS technology and the comparison is made based on speed and power consumed by the circuit. Findings The voltage level shifter circuit discussed in this paper removes the contention problem that is present in conventional voltage level shifter. Moreover, it has the capability for up and down conversion and reduced power and delay as compared to conventional voltage level shifter. The efficiency of the circuit is improved in two ways, first, the current of the pull-up device is reduced and second, the strength of the pull-down device is increased. Originality/value The modified level shifter is faster for switching low input voltage to high output voltage and also high input voltage to low output voltage. The average power consumption for the multi-scaling voltage level shifter is 259.445 µW. The power consumption is very less in this technique and it is best suitable for low-power applications.

A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications

This brief presents a fast and power-efficient voltage level-shifting circuit capable of converting extremely low levels of input voltages into high output voltage levels. The efficiency of the proposed circuit is due to the fact that not only the strength of the pull-up device is significantly reduced when the pull-down device is pulling down the output node, but the strength of the pull-down device is also increased using a low-power auxiliary circuit. Postlayout simulation results of the proposed circuit in a 0.18- $\mu \text{m}$ technology demonstrate a total energy per transition of 157 fJ, a static power dissipation of 0.3 nW, and a propagation delay of 30 ns for input frequency of 1 MHz, low supply voltage level of $V_{\mathrm {{DDL}}}= 0.4$ V, and high supply voltage level of $V_{\mathrm {{DDH}}}= 1.8$ V.

A 65-nm 25.1-ns 30.7-fJ Robust Subthreshold Level Shifter With Wide Conversion Range

Level shifters (LS) are crucial interface circuits for multisupply voltage designs, and it is challenging to achieve both robust and efficient level conversion from subthreshold to aforementioned threshold. In this brief, we propose two circuit techniques for a novel subthreshold LS with wide conversion range. First, we introduce a novel LS circuit with NMOS-diode-based current limiter for current contention reduction to achieve robust and efficient level conversion. Second, we explore the inverse narrow width effect to increase the drivability of the pull-down devices for delay reduction. When implemented in a commercial 65-nm MTCMOS process, the proposed LS achieves robust conversion from deep subthreshold (sub-100 mV) to nominal supply voltage (1.2 V). For the target conversion from 0.3 to 1.2 V, the proposed LS shows on average 25.1-ns propagation delay, 30.7-fJ energy efficiency, and 2.5-nW leakage power across 25 test chips.

A Low-Power Subthreshold to Above-Threshold Voltage Level Shifter

This brief presents a power-efficient voltage level-shifter architecture that is capable of converting extremely low levels of input voltages to higher levels. In order to avoid the static power dissipation, the proposed structure uses a current generator that turns on only during the transition times, in which the logic level of the input signal is not corresponding to the output logic level. Moreover, the strength of the pull-up device is decreased when the pull-down device is pulling down the output node in order for the circuit to be functional even for the input voltage lower than the threshold voltage of a MOSFET. The operation of the proposed structure is also analytically investigated. Post-layout simulation results of the proposed structure in a 0.18-μm CMOS technology show that at the input low supply voltage of 0.4 V and the high supply voltage of 1.8 V, the level shifter has a propagation delay of 30 ns, a static power dissipation of 130 pW, and an energy per transition of 327 fJ for a 1-MHz input signal.

Denser and More Stable SRAM Using FinFETs With Multiple Fin Heights

We present the optimization of multiple-fin-height FinFET static random access memory (SRAM) to reduce cell leakage and improve the stability and density of SRAM. Using a taller fin FinFET for the pull-down device increases the read static noise margin of the SRAM and can potentially reduce the SRAM cell area. A reasonable amount of channel doping in all the transistors can be used to reduce the cell leakage current without appreciably degrading the stability of the SRAM cell. Increasing the channel doping of the access transistor simultaneously improves the read stability and decreases the cell leakage current of the SRAM cell.

Four-Terminal-Relay Body-Biasing Schemes for Complementary Logic Circuits

Four-terminal-relay inverter circuit characteristics are investigated. To achieve maximum noise margin and zero crowbar current while allowing for relay-to-relay variations, the optimal biasing scheme provides for switching that is symmetric about VDD/2 with minimum hysteresis and no possibility of both the pull-down and pull-up devices being on simultaneously.

Compact models considering incomplete voltage swing in complementary metal oxide semiconductor circuits at ultralow voltages: A circuit perspective on limits of switching energy

This paper presents a circuit perspective on complementary metal oxide semiconductor (CMOS) limits by analyzing a standard CMOS inverter driving a capacitive load at ultralow supply voltages. While the behavior of an inverter is well understood and modeled in the superthreshold region and for sufficiently high supply voltages in the subthreshold region, the analysis at ultralow supply voltages is different. In this region of operation, the voltage levels corresponding to logic “1” and logic “0” are not Vdd and Gnd, respectively. We model the incomplete voltage swing and show that the minimum supply voltage for a CMOS inverter (with pull-up and pull-down devices as ideal conventional metal oxide semiconductor field effect transistors) is, indeed, 2kT/q ln 2. The novelty of this approach lies in the fact that it gives an explicit mathematical relationship between the supply voltage and a measure of distinguishability of the binary states defined in terms of the expected voltage swing. The analysis shows that the minimum supply voltage corresponds to the state when the two states become completely indistinguishable. Further, we obtain a relationship between the switching energy and robustness of CMOS inverters and interconnects, valid for the entire range of supply voltages. This analysis also shows that a minimum supply voltage of 2kT/q ln 2 may not correspond to the fundamental energy dissipation of kT ln 2.

Design of H-Bridge Class-D Power Amplifiers for Digital Pulse Modulation Transmitters

This paper presents an H-bridge class-D power amplifier (PA) for digital pulse modulation transmitters. The class-D amplifier can be driven by two-or three-level digital signals generated by a delta-sigma modulator (DSM) and provides a linear microwave output after filtering. Within the amplifier, the pull-up and pull-down devices are driven separately to improve the amplifier efficiency by minimizing the loss associated with shoot-through current. The H-bridge class-D PA system was tested with code-division multiple-access IS-95 signals at 800 MHz. Using binary DSM signals, a drain efficiency of 31% was achieved with an output power of 15 dBm and an adjacent channel power ratio of -43 dBc. With three-level DSM signals, a drain efficiency of 33% was achieved at same output power. An analysis of the factors governing amplifier efficiency is provided.

A Current Estimation Method for Bias-Temperature Stress of a-Si TFT Device

We have studied the time-dependence degradation of ON current of amorphous silicon thin-film transistors (a-Si:H TFTs), which is a function of stress duration, stress temperature, and stress bias. A simple method with stretched-exponential equation and current-voltage function is used to characterize and predict the TFT performance. Bias-temperature stress at different stress voltages has been performed on a-Si:H TFTs. A new method using ON current degradation to analyze TFT device performance is presented, which is different from the conventional threshold-voltage shift method. We have also observed that the beta value in the ON current degradation method compared to the threshold-voltage shift method, with a stretched-exponential stress time, is related to beta~beta <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> -T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ST</sub> /T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> . Finally, we have also used the new equation to evaluate the performance of the gate-driver-on-array circuit in our products. If the limitation of the current for the pull-down device is 1times10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup> A, then the operation time of the pull-down device can be estimated to about 1219 h when key pulled-down TFT is operating at 60degC.

A New Design Scheme for Logic Circuits with Single Electron Transistors

A new design scheme for logic circuits utilizing single electron transistors (SETs) is proposed. First, logic operations are implemented in logic trees composed of SETs used as pull-down devices. Second, the supply voltage to SET logic trees is lower than the gate voltage swing of SETs. Third, a clock control concept similar to that of complementary metal-oxide-semiconductor (CMOS) dynamic logic is utilized. Finally, the output voltages of logic trees are amplified to the same voltage as the gate voltage swing of SETs by the CMOS inverters in order to drive the next gates. It is confirmed by the hybrid simulator of single electron tunneling and SPICE that a SET logic circuit, a four-way exclusive OR, operates perfectly. It is concluded that the proposed SET logic is consistent in voltage levels and is realistic for the hybrid circuits of SETs and CMOS.

A low-noise TTL-compatible CMOS off-chip driver circuit

Low-noise TTL-compatible off-chip driver (OCD) circuits are very important, especially for low-power electronics, but scaled-down CMOS technology requires a lower operating voltage of 3.3 V, while most applications require 5 V. The dual power-supply requirement makes the design of OCD challenging, first because pull-up devices, especially p-MOS devices, must be able to handle an off-chip voltage of 5.6 V, which is higher than an on-chip VDD of 2.8 V, and second because pull-down devices should be able to discharge a capacitive load of 5.6 V while operating at a minimum on-chip VDD of 2.8 V. This extreme difference in operating voltage makes the circuits susceptible to ringing and performance degradation due to hot-electron effects. In this paper, we describe a low-noise OCD which has been successfully used in IBM second-generation 4Mb low-power DRAM (LPDRAM) and in other products. For pull-ups, two stacked p-MOS devices with floating n-wells are used, but they are operated in different modes dependi ng on the supply voltage. The pull-down devices are basically composed of two stages, one of which is in the diode configuration with its gate and drain shorted together during the pull-down. Detailed circuit designs to achieve low noise while meeting the performance requirements are described.

Three-dimensional numerical simulation of single event upset of an SRAM cell

Charge collection mechanisms in PMOS and NMOS transistors irradiated by single energetic ions and the corresponding response of an SRAM (static random-access memory) cell have been simulated. For an ion track through a p-channel, the RC network within the cell and the strength of the n-channel pull-down device will limit the amount of charge collected. In the case of the n-channel pull-down device, the direction of the ion strike (toward or away from the source) plays a major role in the upset of the cell. An ion path toward the source upsets at a lower LET (linear energy transfer) than one away from the source. This is the result of additional electrons injected from the source due to barrier lowering.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

2.5-V bipolar/CMOS circuits for 0.25- mu m BiCMOS technology

An ECL circuit with an active pull-down device, operated from a CMOS supply voltage, is described as a high-speed digital circuit for a 0.25- mu m BiCMOS technology. A pair of ECL/CMOS level converters with built-in logic capability is presented for effective intermixing of ECL with CMOS circuits. Using a 2.5-V supply and a reduced-swing BiNMOS buffer, the ECL circuit has reduced power dissipation, while still providing good speed. A design example shows the implementation of complex logic by emitter and collector dottings and the selective use of ECL circuits to achieve high performance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A Method of Perforating Casing Below Tubing

Abstract The introduction in the field of a new type well completion called for the setting of tubing open-ended in the well before perforating the casing. This paper describes a new perforating tool of the shaped charge expendable type, small enough to pass through tubing and powerful enough to perforate the casing. The perforations are produced at an angle and are large enough for optimum production. Performance of this tool in targets and under various well conditions is described. Very often no lifting equipment will be available at the well. In some cases, pressure will exist in the well at the time of the perforating operation (workover wells or multiple trip perforation); therefore, new equipment and new technique for the perforating operation were devised. This paper describes this equipment and technique, particularly casing collar recording, sheave support, and cable pull-down device, this last item being necessary for wells under pressure. Results obtained with this tool in the field are given. Introduction One of the key requirements for the introduction in the field of a new method of permanent well completion was the development of a new perforating method involving the use of a perforating gun small enough to go through tubing and with enough penetrating power to perforate the casing satisfactorily. The equipment described in this paper was basically designed to go through open-ended two-in. tubing and to perforate 5?-in. casing. The equipment is illustrated in accompanying figures. New Completion Method With the new permanent type well completion, the production string of casing is run and cemented through the potential producing zone. Open-ended tubing is then run into the well and used to replace the drilling fluid with oil or water. The amount of the oil or water "cushion" can be varied according to the expected bottom hole pressure. Thus, if desired, the hydrostatic head can be greater, equal to, or less than the expected pressure within the zone to be perforated. Mud having been displaced, the tubing is then positioned so that the end is above the zone to be perforated.