PSPICE Simulation Research Articles

VDTA-based floating/grounded series/parallel R-L and R-C immittance simulators with a single grounded capacitor

Active configurations for simulating floating/grounded series and parallel immittance functions based on voltage differencing transconductance amplifiers (VDTAs) are proposed. The grounded series and parallel immittance simulators presented here require only one VDTA, while the proposed floating ones only need two. Each of the suggested simulators uses a single grounded capacitor. The proposed topologies can imitate R-L and R-C immittances in both series and parallel types. All of the simulated equivalent elements are electronically adjustable through the VDTA’s transconductance. Furthermore, no component-matching restrictions are imposed in order to achieve the appropriate immittance function. Applications of the proposed VDTA-based immittance simulators include bandpass filter and quadrature oscillator implementations. The behaviors of the proposed circuits and their applications are evaluated by PSPICE simulations and experimental observations using VDTA implemented with commercially available CA3080 type OTAs.

Design of Current-Mode versatile Multi-Input analog multiplier topology

In this paper, a novel n-input 2n orthant class-AB current-mode multiplier topology is presented. The proposed analog current-mode multiplier is implemented by using two basic blocks, which are a current splitter and a one-quad multiplier. These blocks are based on the translinear circuit principle. Moreover, the designed multiplier can be easily extended for multi-input structures. Many different scenarios presenting particular usage of the proposed multiplier structure are presented as well. The functionality of all the proposed circuits utilized in different cases is verified by using the PSpice simulation program, where 0.13 μm IBM CMOS technology parameters are employed. The simulation results show that 0.225 mW power consumption and under 3 % Total Harmonic Distortion are observed for the two-input circuit. Furthermore, the bandwidth and the dynamic range of the proposed circuit for the three-input circuit are 165 MHz and 29.54 dB, respectively.

Complex dynamics in a novel jerk system with septic nonlinearity: analysis, control, and circuit realization

This work proposes a new chaotic jerk system with septic nonlinearity. The new system presents odd symmetry and undergoes typical behaviors including period doubling, merging crisis, spontaneous symmetry breaking, coexisting attractors and coexisting bubbles of bifurcations as well. The most gratifying feature discovered in this article, is the occurrence of up to eight coexisting attractors for appropriate sets of parameters. This latter feature is uncommon for a chaotic system as simple as the model proposed in this work (e.g. not reported in cubic, quintic or hyperbolic sine models). Multistability control is achieved by following the linear augmentation approach. We numerically prove that the multistable septic chaotic system can be adjusted to develop a monostable behavior when smoothly monitoring the coupling strength. More interestingly, it is found that the coupling breaks the symmetry of the chaotic jerk system and thus induces new patterns including asymmetric Hopf bifurcations; coexisting non-symmetric bubbles, critical phenomena, coexisting multiple asymmetric attractors, just to name a few. On this line, the linear augmentation scheme can be regarded as a simple means for inducing new features in odd symmetric chaotic systems. PSPICE simulation results captured from an electronic analog of the proposed septic jerk system are consistent with the theoretical investigations.

Research on Compact Nanosecond High-voltage Pulse Source

With the application of pulse power technology in the fields of biomedical research, portable pulse source, and electromagnetic pulse radiation, the research of pulse sources puts forward new requirements such as compact structure, long pulse width, and high voltage resistance. The traditional pulse source has a long pulse period and short pulse width, which cannot meet the requirements of the high repetition frequency and high output power. In this paper, a nanosecond high-voltage pulse source is designed, which consists of a primary power supply, a pulse charging system, and a pulse shaping system. The DC power charges the Marx generator, while the Marx generator output is shaped by short-circuit sharpening switches. In this paper, PSpice simulation software is used to simulate the results: the pulse period is 1.4ns and the peak-to-peak voltage is 210kV.

Memristive Recurrent Neural Network Circuit for Fast Solving Equality-Constrained Quadratic Programming With Parallel Operation

Equality-constrained quadratic programming (QP) has been one of the most basic and typical problems in the Internet of Things domain. In big data scenarios, how to quickly and accurately solve the problem in hardware has not been realized. Therefore, in this article, a memristive recurrent neural circuit that can parallel solve the QP problem in real time is proposed. First, a new memristive synaptic array is designed that can simultaneously implement parallel reading and writing. On the basis of this structure, a new neural network circuit based on memristor is designed that can perform large-scale recursive operations by parallel methods. This circuit can solve the equality-constrained QP problem in different situations by using such real-time programmable memristor arrays processing in memory. The PSpice simulation results show that the problem can be solved with 99.8% precision. Based on practical verification, the neural circuit experiment on PCB is presented with 97.34% precision. Moreover, the circuit has good robustness under the interference of weight value. And, it has an advantage in processing time compared with FPGA.

Single Stage Active Power Factor Correction Circuit for Street LED Light with Battery Backup

This paper proposes a single-stage active power factor correction circuit for street LED light with battery back-up. The buck–boost converter and flyback converter are combined to achieve optimal performance. The first part of the integrated LED driver, the buck–boost converter is used to adjust the power while operating in the discontinuous conduction operation. The second part of the driver, the flyback converter provides regulated voltage to the LEDs. The battery backup circuit charges the battery when ac input power is available and provides power to LED lamp when input power supply is not available. The proposed LED driver was designed for 100 W output power and tested by PSpice simulation. The simulation results obtained are given in the paper to demonstrates the functionality of the proposed LED driver system. The result show good operation and performance of proposed LED driver.

A Universal PSpice Simulation Model of a Switched Buck Voltage Regulator

The article describes the design of a universal simulation model of a voltage regulator for applications compatible with the globally used PSpice program. Users can create a model of any type of integrated switching voltage regulator that is currently available on the market by setting its individual parameters. The proposed connection of the regulator was applied in the connection of the buck DC–DC converter. The accuracy of the model was verified by comparing the results obtained by the simulation to other official models and to practical measurements taken on a real sample of the converter. The versatility of the model was proven by comparison with another type of converter with different parameters.

Multiscroll in Bidirectionally Coupled Jerk Oscillators: Theoretical Analysis and PSpice Verification

It is known that the unidirectional coupling between a double-scroll system (drive) in the oscillation regime with another system (response) in the steady-state, gives rise to more complex dynamics such as multiscroll attractors [Dana et al., 2008]. This paper shows the way to move from n-scroll to 2n-scroll in a bidirectional coupling scheme between two jerk oscillators. The coupling considered can be interpreted as a perturbation to each oscillator’s amplitude through a signal proportional to the amplitude of the other. Indeed, starting from a situation of two oscillators which can generate double-scroll dynamics individually, we perform a bidirectional coupling of both oscillators which results in more complex dynamics such as multistability and 4-scroll chaotic attractor in the coupled system (not observed in an isolated oscillator). The underlined coupling scheme provides an efficient method for generating higher-order multiscroll attractors. The route to the 4-scroll chaotic attractor is explained with the help of bifurcation diagrams, plots of several phase portraits, and basins of attractions. Indirect validation of the theoretical analysis is carried out by using the PSpice simulation software.

Resistorless First-Order Universal Filter Structures Employing OTAs with Independent Controllability of Gain and Pole Frequency

This communication presents two new first order universal active filter configurations employing operational transconductance amplifiers (OTA) and use grounded capacitor which is prominently suitable for integrated chip (IC) fabrication. One of the proposed topologies provides voltage mode (VM) and transconductance mode (TCM) of operations while the other circuit provides current mode (CM) in addition with transresistance mode (TRM) filter functions. All three first order filter functions namely low pass filter (LPF), high pass filter (HPF) and all pass filter (APF) are configurable with appropriate choice(s) of input voltage/current signals. An equal transconductor condition (which can be easily achieved) is required for the realization of APF functions. The proposed filter configurations possess high input impedance and high output impedance and also offer independent electronic tunability of pole frequency/cut-off frequency. The gain of filters realized in VM, TCM and TRM has independent electronic tunability feature and can be adjusted through transconductor. For the usability of proposed filters, multi-phase sinusoidal oscillator has also been demonstrated. To assure the workability of the proposed filter structures, PSPICE simulations with CMOS OTA implemented in 0.18 µm TSMC technology parameters has been used. Various simulation results including Monte-Carlo simulations, process corner analysis, total harmonic distortions (%THD) and temperature analysis have also been appended. Experimental results employing off-the-shelf IC LM13700 type OTAs have also been included to verify the theoretical propositions of first order universal filters and multiphase sinusoidal oscillators.

Electronically Adjustable Multiphase Sinusoidal Oscillator with High-Output Impedance at Output Current Nodes Using VDCCs

This paper presents the high-output-impedance current-mode multiphase sinusoidal oscillators (MSO) using voltage differencing current conveyor (VDCC)-based lossy integrators, which consist of one VDCC, one grounded capacitor, and two grounded resistors. The proposed oscillator can provide an odd-phase and even-phase system without the use of an additional amplifier. The frequency of oscillation (FO) is electronically tuned via the bias current without affecting the condition of oscillation (CO). The proposed oscillator is designed to obtain three-phase sinusoidal waveforms (n = 3). The effect of non-idealities of VDCC on the lossy integrator section is also investigated. The validity of the proposed circuit is demonstrated by PSPICE simulation using 0.18 µm TSMC CMOS process parameters with ±0.9V power supply. The frequency of oscillation obtained from the simulation is 1.43 MHz. The total harmonic distortions of the sinusoidal output currents IO1, IO2, and IO2 are 1.22%, 1.18%, and 0.57%. The IO1–IO2 and IO2–IO3 phase differences are approximately 121 and 119 degrees, respectively. The feasibility of the proposed MSO is also verified with experimental results using the VDCC constructed from the commercially available ICs (LT1288 and AD844) with ±5 V power supply. The results of PSPICE simulations and experiments are closely consistent with the theoretical expectation.

Extremely rich dynamics of coupled heterogeneous neurons through a Josephson junction synapse

Artificial neural networks are generally used to emulate some biological activities of the brain. Those neurons in the network are connected to others through synapses. As a result, several works have been devoted to the design of various artificial synapses, including the Josephson Junction Synapse (JJS). In this contribution, a model of the Hindmarsh–Rose neuron coupled with a FitzHugh–Nagumo neuron through a JJS is considered. That JJS enables us to simulate the effects of the magnetic field by providing additional phase error between the junctions. The Hamilton function related to the energy released by the coupled neurons during the transition between electrical activities is determined using the Helmholtz theorem. The equilibrium points of the proposed model are investigated, and their stability justifies the self-excited dynamics of the model. During studies, sets of phenomena such as Hopf bifurcation, double Hopf bifurcation, periodic spikings, periodic and chaotic burstings, (resp. firings) are found. More importantly, several coexisting activities are found in the coupled neurons as well as hyperchaotic firing activities rarely reported in such classes of neurons. Finally, PSpice simulations are used to further support results obtained from the mathematical model of coupled neurons through a JJS.

Electronically and Independently Controllable Quadrature Sinusoidal Oscillator with Low Output Impedances

This work presents the quadrature sinusoidal oscillator using two Voltage Differencing-Differential Input Buffered Amplifiers (VD-DIBAs), two resistors, and two capacitors. The VD-DIBA is an electronically controllable active building block with high input and low output impedances that can connect to other circuits directly without the buffers. With these distinguished features, the VD-DIBA is employed in this design. The proposed oscillator can produce two sine waves with a phase shift of 90 degrees. Over the entire tuning frequency range, the magnitude of the quadrature output voltages is constant. The proposed oscillator is independently adjustable in terms of frequency and oscillation condition. Moreover, the frequency of oscillation can be electronically and linearly adjusted by the bias currents. The condition of oscillation is adjustable by resistors, R_1 and R_2. The performances of the proposed quadrature oscillator are tested through the PSpice simulation and the experiment. In the simulation, the VD-DIBA is built from the 0.18um Taiwan Semiconductor Manufacturing Company (TSMC) CMOS process with +-0.9V supply voltages. In the experiment, the VD-DIBA is implemented using the commercial ICs, LM13700, and AD830 with +-5V supply voltages. The simulated Total Harmonic Distortion (THD) values of the output voltages, V_o1 and V_o2 at f_0 = 1.03MHz are 1.63% and 1.81%, respectively. The experimental THD values of the output voltages, V_o1 and V_o2 at f_0 = 536.6kHz, are 1.43% and 1.00%, respectively.

Memristive competitive hopfield neural network for image segmentation application.

Image segmentation implementation provides simplified and effective feature information of image. Neural network algorithms have made significant progress in the application of image segmentation task. However, few studies focus on the implementation of hardware circuits with high-efficiency analog calculations and parallel operations for image segmentation problem. In this paper, a memristor-based competitive Hopfield neural network circuit is proposed to deal with the image segmentation problem. In this circuit, the memristive cross array is applied to store synaptic weights and perform matrix operations. The competition module based on the Winner-take-all mechanism is composed of the competition neurons and the competition control circuit, which simplifies the energy function of the Hopfield neural network and realizes the output function. Operational amplifiers and ABM modules are used to integrate operations and process external input information, respectively. Based on these designs, the circuit can automatically implement iteration and update of data. A series of PSPICE simulations are designed to verify the image segmentation capability of this circuit. Comparative experimental results and analysis show that this circuit has effective improvements both in processing speed and segmentation accuracy compared with other methods. Moreover, the proposed circuit shows good robustness to noise and memristive variation.

Design of Winner-Takes-All Circuits in Competitive Neural Networks

The Winner-Take-All circuit is an important part of the competition layer in the competitive neural network. Its main function is to compare the size of the output of the nodes after the weighted summation of all input vectors, and select the node with the largest output to output high power level, while other nodes output low level, that is, to find the node with the largest output. According to the characteristics of the Winner-Take-All circuit in the competitive neural network, the simulation of the Winner-Take-All circuit is carried out by the PSPICE simulation software. The physical test results show that, like the simulation diagram of the Winner-Take-All circuit, it conforms to the logic truth table, which further confirms the rationality and correctness of the Winner-Take-All circuit. Hardware realization of Winner-Take-All circuit as an important component of competitive layer in competitive neural networks has important research significance.

Single MEXCCII-Based Grounded Immittance Functions Simulation and Applications

A simple circuit based on modified extra-X second-generation current conveyor (MEXCCII), which is capable of realizing the following grounded immittance functions: a lossless capacitor, a lossy capacitor, a lossy inductor and a lossy frequency-dependent negative conductance, is introduced in this paper. The circuit employs one MEXCCII and three passive components. The use of single active block makes the circuit structure simpler. No component’s matching constraint is needed in the proposed circuit. The nonideal study of the proposed grounded immittance circuit is also included. The circuit’s performance is examined using 0.18-[Formula: see text]m technology-based PSPICE simulations. Experimental results which are performed using off-the-shelf integrated circuits (ICs) and bread board are also included. The proposed circuit is negligibly affected by the temperature variation and process variation. A single pole high-pass filter as an application of the realized lossy capacitor and a band-pass filter as an application of the realized lossy inductor are also presented in this paper. The realized filters offer the feature of ease of cascadability.

A Modern VDCCTA Active Element and Its Electronic Application

In this paper, a novel current mode (CM) building block termed Voltage differencing current conveyor transconductance amplifier (VDCCTA) is developed by combining the voltage differencing current conveyor (VDCC) and an operational transconductance amplifier (OTA). This modern active block VDCCTA is extended for applications such as a lossless inductor, filter design, and chaotic circuit design. An active inductor simulator (AIS) without any component matching is designed using the proposed VDCCTA block and a grounded capacitor as a first application that offers flexibility to model grounded positive active inductor (GPAI), grounded negative active inductor (GNAI), and floating positive active inductor (FPAI) circuits. Moreover, the proposed positive active inductor (PAI) can also be translated for multiple input single output (MISO) voltage mode (VM) universal filter with two external passive elements and chaotic circuitry. The characteristics of VDCCTA are verified with the CM multifunction filter, VM band-pass filter, and VM-MISO filter. A complete exercise of this newly reported VDCCTA block is analyzed for their port characteristics validation and the performance parameters using PSPICE simulation. Finally, experimental verification of the proposed AIS is tested to justify the theoretical and simulated results.

An Offset-Boostable Chaotic Oscillator with Broken Symmetry

A new 3D offset-boostable symmetric system is proposed by an absolute value function introduced. The system seems to be more fragile and easier to the state of broken symmetry. Coexisting symmetric pairs of attractors get closer and closer, and finally get emerged together. Basins of attraction show how these coexisting attractors are arranged in phase space. All these coexisting attractors can be easily offset boosted in phase space by a single constant when the initial condition is revised accordingly. PSpice simulations prove all the phenomena.

A low voltage low power CMOS gm-C first order all pass filter

ABSTRACT A low voltage gm-C first order all pass filter circuit is given which uses only two CMOS inverter-based transconductance elements and a capacitor in its realisation. The circuit provides first order all pass filter response without any passive component matching constraints. It uses low component count, possesses low incremental sensitivity, low power consumption and is compatible for monolithic implementation in CMOS technology. The filter is designed and verified using PSPICE simulation. The results on the realised filter verify the theory.

Resistorless Chua's diode implementation for chaotic oscillation employing single EXCCCII

A passive resistor-free Chua’s Diode with smooth nonlinearity is introduced using a single Extra X Current Controlled Current Conveyors (EX-CCCII). The proposed Chua’s Diode can generate all fundamental Chua’s chaotic responses like Rossler type attractor, double scroll attractor, and large limit cycle. Chua’s chaotic response can be easily observed in two ways: (i) by tuning the bridging resistor between two capacitors present in a Chua's circuit and (ii) by adjusting the bias current of EX-CCCII present in the proposed Chua’s diode. The proposed Chua’s model is verified with three possible combinations: Chua’s oscillation with a passive inductor, tunable Chua’s oscillation by varying the bias current present in EX-CCCII based negative resistance, and inductor less Chua’s circuit using active inductor based on EX-CCCII. Moreover, the effect of non-idealities present in EXCCCII on negative resistance and dynamical investigation of theproposed Chua’s circuit is described for better understanding. The functionality of the proposed Chua’s circuit is well verified through PSPICE simulation using 0.25 μm TSMC CMOS technology parameters and Current Feedback operational amplifier (CFOA) as IC AD844 based EX-CCCII. In addition to computer simulation, an experimental investigation is also performed by CFOA as IC AD844 to realize EX-CCCII. Finally, a comparison between the existing Chua’s circuit and the proposed one is illustrated for a fair comparison.

Wave Active Low Pass Filter Employing Modern Active Block VDDIBA

This paper presents a second and third-order wave active low pass filter (WALPF) using modern active block Voltage Differencing Differential Input Buffered Amplifier (VDDIBA) with a lower supply voltage of 1V. The wave-active approach is chosen for the filter designing to get a higher order, lower sensitivity, modular and stable filter structure. The design procedure of WALPF involves the implementation of wave-active equivalent for series inductor and shunt capacitor. And it needs to realize the subtractor block physically, and the lossy subtractor integrator block using VDDIBA gives a flavor of differencing voltage property. So, the physical implementation of the subtractor block and the lossy subtractor integrator block goes very smoothly using this block. It is considered a possible reason for reducing active blocks and passive components. Theoretical justification of the proposed WALPF is achieved by using the wave-equivalent concept of the wave-active approach. This method of WAF design consists of only one resistor and capacitor, making the filter structure less complex easy to use with a cut-off frequency of 10MHz. Finally, the workability test is examined with the PSPICE simulation that results in the WALPF frequency response using 180 nm TSMC CMOS technology parameter for VDDIBA.