Pseudomorphic High Electron-mobility Transistor Technology Research Articles

A Ku-Band GaAs Multifunction Transmitter and Receiver Chipset

This paper presents a Ku-band monolithic multifunction transmitter and receiver chipset fabricated in 0.25-μm GaAs pseudomorphic high-electron mobility transistor technology. The chipset achieves a high level of integration, including a 4-bit 360° digital phase shifter, 5-bit 15.5-dB digital attenuator, amplifier and 9-bit digital serial-to-parallel converter for digital circuit control. Since the multifunction chipset includes a medium power amplifier and a low-noise amplifier, it features high P1dB and low noise figures over the full Ku-band frequencies. The multifunction transmitter shows a peak gain of 16.5 dB with output P1dB of 19.2 dBm at 15 GHz. The multifunction receiver shows a peak gain of 17.3 dB with noise figure of 2.5 dB at 15 GHz. The attenuation range is 15.5 dB with a step of 0.5 dB and the phase shift range is 360° with a step of 22.5°. Each chip area of the transmitter and receiver is 4.2 × 2.8 mm2.

Resonance gate bias cascode class-E power amplifier in GaAs pHEMT technology

In this paper, switching behavioural of cascode transistor in class-E cascode structure is improved by resonance gate bias (RGB) technique. The proposed technique can be used to increase supply voltage of a cascode class-E power amplifier (PAs) in order to achieve high output power and efficiency. Output power of class-E PAs are limited due to drain–gate stress caused by the switching transient voltages. The RGB technique relaxes the supply voltage limitation due to breakdown voltage (VBD) of the transistor. In addition, reactance compensation components technique is employed to achieve high-power and wide-band class-E PA. To show validity of the proposed RGB technique, two reliable 1-W high-voltage and high-efficiency class-E PAs are fabricated in a 0.25 μm GaAs pseudomorphic high-electron mobility transistor technology. The 1.8 GHz class-E PA achieves 52% power added efficiency (PAE) and 30.6 dBm output power. The designed 2–3 GHz class-E PA has 45% PAE at output power of 30 dBm.

A 270 GHz × 9 Multiplier Chain MMIC With On-Chip Dielectric-Resonator Antenna

This paper presents a 270 GHz × 9 multiplier chain with on-chip dielectric-resonator antenna (DRA) developed in a commercial 0.1- μ m GaAs pseudomorphic high electron-mobility transistor technology with cutoff frequencies $f_{{\rm{T}}}\, / f_{{\rm{MAX}}}$ of 130/180 GHz. The multiplier integrates a W-band tripler followed by a driver amplifier, a J-band tripler, and an on-chip antenna. The multiplier breakout achieves a measured peak output power of –4 dBm at 270 GHz and a 3-dB bandwidth of 40 GHz (from 255 to 295 GHz). By introducing the high-pass matching network into the multiplier design, the in-band unwanted harmonic suppression is improved to be over 40 dBc within the entire bandwidth. The higher order mode (TE δ 13 mode) dielectric resonator is introduced in the on-chip antenna design to enhance the antenna gain and bandwidth without additional chip area consumption. The multiplier chain with the on-chip DRA has a measured EIRP of +2 dBm at 270 GHz and a 3-dB bandwidth of 33 GHz (from 258 to 291 GHz). Compared with other J-band multipliers, this paper achieves the best spurious suppression and comparable output power while using the technology with the lowest cutoff frequencies.

A 1.5–45-GHz High-Power 2-D Distributed Voltage-Controlled Attenuator

We present the development of an ultra-wideband and 1-W voltage-controlled attenuator (VCA) using a 0.15- $\mu \text{m}$ enhancement mode gallium arsenide pseudomorphic high-electron mobility transistor technology. For the first time, a 2-D stacked field-effect transistor configuration is employed in a distributed VCA to simultaneously achieve wide bandwidth, high power, high dynamic range, and low insertion loss. The systematic design methodology is proposed, and a VCA prototype is fabricated and measured for verification. The monolithic microwave integrated circuit (MMIC) VCA exhibits a measured insertion loss of 1.9–5.5 dB from 1.5–45 GHz. The measured highest input 1-dB power compression point ( $P_{\mathrm {1dB}}$ ) is 30 dBm with a dynamic range of 26 dB. To the best of the authors’ knowledge, this paper reports the highest bandwidth and $P_{\mathrm {1dB}}$ of a single MMIC VCA while still maintaining excellent performance regarding dynamic range, insertion loss, and chip size.

Design and Analysis of a $Ka$-Band Monolithic High-Efficiency Frequency Quadrupler Using GaAs HBT–HEMT Common-Base/Common-Source Balanced Topology

A Ka-band monolithic high-efficiency frequency quadrupler using a GaAs heterojunction bipolar transistor and pseudomorphic high electron-mobility transistor technology is presented in this paper. The frequency quadrupler is constructed cascading two frequency doublers. The frequency doubler employs a modified common-base/common-source topology to enhance the second harmonic efficiently. The dc bias condition, harmonic output power, conversion gain, and efficiency for variable configurations are investigated. Two phase-shifter networks are used to reduce phase error and improve the fundamental rejection. Between 23-30 GHz, the proposed frequency quadrupler features a conversion gain of higher than -1 dB with an input power of 4 dBm. The maximum conversion gain is 2.7 dB at 28 GHz with an efficiency of up to 8% and a power-added efficiency of 3.6%. The maximum output 1-dB compression point (P1 dB) and the saturation output power (Psat) are higher than 7 and 8.2 dBm, respectively. The overall chip size is 2×1 mm2.

V-Band High Data-Rate I/Q Modulator and Demodulator With a Power-Locked Loop LO Source in 0.15-/spl mu/m GaAs pHEMT Technology

A wideband sub-harmonically pumped (SHP) modulator and demodulator fabricated in 0.15-μm GaAs pseudomorphic high electron-mobility transistor technology are demonstrated in this paper. The chip is appropriate for emerging 60-GHz multi-gigabit communication applications. Digital modulation degradation resulting from in-phase/quadrature mismatch is effectively minimized by the proposed power-locked loop system. By overcoming the bandwidth limitations and quadrature errors in amplitude and phase, the sideband suppression ratio exhibits broadband performance with the feedback mechanism. By using the SHP mixer structure, the dc offset problem is mitigated because of decreased 2× local oscillator leakage. In addition, sub-circuit design considerations and feedback stability are described in this paper. The SHP modulator and demodulator demonstrate flat conversion-gain responses of -14 ±2 dB and -14 ±1 dB, respectively, from 51 to 68 GHz. Properties of multi-gigahertz modulation and demodulation bandwidths show the potentials for gigabit applications. The amplitude and phase imbalances are restricted within 0.3 dB and 5° (±2.5°), respectively, regardless of modulation or demodulation. High data-rate digital modulation and demodulation are successfully performed through 16-QAM and 64-QAM schemes within four channels of the IEEE 802.15.3c standard with outstanding error vector magnitude performances.

Low phase noise V-band push–push voltage controlled oscillator using 0.15 [micro sign]m GaAs pseudomorphic high electron-mobility transistor technology

A low phase noise, low dissipated power and small-size V-band voltage-controlled oscillator (VCO) using dual cross-coupled pair configuration, capacitance-splitting technique and push–push topology is presented. The V-band VCO circuit uses 0.15 µm GaAs pseudomorphic high electron-mobility transistor technology. The VCO has low phase noise, of −108.43 dBc/Hz, at a 1 MHz offset from a 62 GHz carrier and can be tuned from 61.11 to 62.66 GHz. The figure of merit is −190.45 dBc/Hz. The power consumption of the VCO with 1.04 mm2 chip area is 24 mW, from a 1 V power supply.

A 9.1–10.7 GHz 10-W, 40-dB Gain Four-Stage PHEMT MMIC Power Amplifier

This letter presents a compact X-band high gain and high power four-stage AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) monolithic microwave integrated circuit (MMIC) high power amplifier (PA). This amplifier is designed to fully match a 50-Omega input and output impedance. Based on 0.35-mum gate-length power PHEMT technology, this PA MMIC is fabricated on a 3-mil thick wafer. While operating under 8 V and 2700-mA dc bias condition, the characteristics of 40-dB small-signal gain, a 10-W continuous-wave saturation output power, and 33% power added efficiency at 9.7GHz can be achieved

A 45-dB variable-gain low-noise MMIC amplifier

A variable-gain amplifier (VGA) operating at 2.5 GHz based on single-ended topology has been designed and characterized. Three such stages were cascaded and preceded by a single-stage low-noise amplifier. A source follower was used at the output in order to achieve excellent output match. The variation gain is 45 dB with a maximum gain of 47 dB. The -3-dB bandwidth is 0.8 GHz. Minimum noise figure of 0.81 dB is obtained in the highest gain mode. The highest output power, corresponding to 1-dB compression point is -7.2 dBm and the corresponding output third-order intercept point is +2 dBm. The circuit is implemented in a GaAs 0.15-mum pseudomorphic high electron-mobility transistor technology. The combined area occupied by the multistage low-noise VGA and the single-ended VGA is 3.5 mm times 3 mm

10-Gb/s driver amplifier using a tapered gate line for improved input matching

The use of a tapered gate line in a distributed amplifier (DA) is investigated and applied to the design of a GaAs monolithic microwave integrated circuit 10-Gb/s optical driver amplifier. Improved input matching is achieved near the cutoff frequency by reducing the characteristic impedance successively along the gate line toward the termination. With the improved matching conditions, the voltage ripple on the final resistor termination is reduced. The degree of tapering that can be employed is limited by the low-frequency gain and matching requirements. Detailed analysis and simulation results are used to investigate the advantage of this technique. To demonstrate its practical use, the performance of a 10-Gb/s DA fabricated with Filtronic Compound Semiconductor's 0.5-/spl mu/m pseudomorphic high electron-mobility transistor technology is presented.

40-Gb/s wide-band MMIC pHEMT modulator driver amplifiers designed with the real frequency technique

With the use GaAs pseudomorphic high electron-mobility transistor technology, the bandwidth performances of Cherry-Hooper driver amplifiers need to be improved. To fulfill these requirements, we propose an original driver circuit topology dedicated to 40-Gb/s optical communication systems. To flatten the transducer gain response of the circuit, passive networks have been added in the design. These networks have been optimized by means of the real frequency technique (RFT). A modified procedure of the classical RFT is introduced to perform the optimization in the presence of an overall resistive feedback.

High-gain frequency-tunable low-noise amplifiers for 38-42.5-GHz band applications

High-performance tunable low-noise amplifiers for 38-42.5 GHz applications are presented based on a fully stabilized GaAs pseudomorphic high electron mobility transistor (PHEMT) 0.2 μm technology. A single 1.5×3 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip, incorporating six amplifying stages, shows a measured gain of 36-42 dB depending on the center frequency. Both maximum gain frequency and input impedance of the amplifier are accurately tunable on the chip. This means that the amplifier provides a narrow-band filtering function and can be matched to a fast p-i-n photodiode as well as to a 50 /spl Omega/ load. This is the first time such performances are reported for single chip narrow-band tunable amplifiers using a GaAs PHEMT technology.

Cryogenic characteristics of wide-band pseudomorphic HEMT MMIC low-noise amplifiers

Two wideband (8-18-GHz) single-stage MMIC (monolithic microwave integrated circuit) low-noise amplifiers (LNAs) using 0.2- mu m T-gate InGaAs pseudomorphic HEMT (high-electron-mobility transistor) technology, designed and fabricated for room temperature operation, were evaluated and compared at cryogenic temperatures below 20 K. One is a balanced design using 3-dB Lange couplers, and the other is a feedback design using a series RLC parallel feedback network. The gain flatness over the 8-18-GHz frequency band was maintained for both amplifiers at room and cyrogenic temperatures, indicating that the topology for wideband designs is insensitive to temperature of operation. As the physical temperature decreased from 297 K to below 20 K, the balanced LNA exhibited an average gain increase of 2 dB and as much as an eightfold reduction of noise temperature to 20 K, while the feedback LNA exhibited an average gain increase of less than 1 dB and an average foufold reduction of noise temperature to 50 K. The negative feedback network of the feedback LNA resulted in less gain increase and less noise temperature reduction at cryogenic temperatures. >