Pseudomorphic High Electron-mobility Transistor Process Research Articles

Analysis and Design of a Gain-Enhanced 1–20-GHz LNA With Output-Stage Transformer Feedback

A gain-enhanced technique with output-stage transformer feedback (OSTF) for the low-noise amplifiers is proposed in this brief. The transformer is realized by a pair of magnetically coupled microstrip lines between the drain and source stages, one of which acts as a series-peaking inductor and the other as a source degenerate inductor. By adjusting the length and gap of the magnetically coupled microstrip lines, the tuning of the gain in high frequency is realized. To verify the proposed OSTF gain-enhanced scheme, two LNAs with the same structure are designed, with one having OSTF and the other not. The gainenhanced wideband LNA with OSTF is fabricated in 0.15-GaAs pseudomorphic high-electron mobility transistor process. The total chip area, including input and output testing pads, is 1.24 mm2. The simulated results show excellent performance with a maximum gain improvement of 3-dB at 20 GHz. The measured results show that the gain-enhanced LNA has an average gain of 22.6 dB and a noise figure below 2 dB from 1 to 20 GHz, which are in good agreement with simulated ones.

Analysis and Design of a 0.1–23 GHz LNA MMIC Using Frequency-Dependent Feedback

In this brief, a 0.1 to 23 GHz low-noise amplifier (LNA) employing a frequency-dependent feedback loop (FDFL) is presented. As predicted theoretically, the optimized FDFL enhances the bandwidth and the gain flatness in desired frequency band through purposely designing the feedback characteristics from negative to positive corresponding to the frequency. Based on the theoretical analysis of bandwidth enhancement, noise characteristic, and linearity of FDFL, an ultra-broadband LNA, utilizing the proposed technique, is designed and verified experimentally by a three-stage LNA chip implemented using a 0.15- $ {\mu }\text{m}$ GaAs pseudomorphic high electron-mobility transistor process. Measurement results show that the LNA obtains an average gain of 27.4 dB and noise figure of 2.7 to 4 dB in a frequency band from 0.1 to 23 GHz, with a compact chip area of only 1.36 mm2, including input/output testing pads.

An Energy-Efficient <inline-formula> <tex-math notation="LaTeX">$Ka$ </tex-math> </inline-formula>/<inline-formula> <tex-math notation="LaTeX">$Q$ </tex-math> </inline-formula> Dual-Band Power Amplifier MMIC in 0.1-<inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math> </inline-formula>m GaAs Process

An energy-efficient ${Ka}$ / ${Q}$ dual-band power amplifier (PA) is proposed using 0.1- $\mu \text{m}$ GaAs pseudomorphic high-electron mobility transistor process in this letter. The PA consists of two stages, and its high efficiency is enhanced by employing a low-loss dual-band output matching network, and adopting different supply voltages for the driver stage and the output stage. Owing to the proposed matching circuits, the PA achieves a measured small signal gain of 19.3 and 15.5 dB, output power of 22.5 and 22.7 dBm, and peak power-added efficiency of 38% and 40% at 29.5 and 47 GHz, respectively. To our best knowledge, this is the state-of-the-art high efficiency dual-band PA operating at ${Ka}$ -band and ${Q}$ -band.

DC‐16 GHz GaAs track‐and‐hold amplifier using sampling rate and linearity enhancement techniques

A DC-16 GHz track-and-hold amplifier (THA) using 0.15-μm enhancement-mode GaAs pseudomorphic high-electron mobility transistor process is presented. A switched source follower (SSF) track-and-hold (T/H) stage is modified to enhance the sampling rate and linearity. The input-dependent timing jitter is highly reduced using the modified topology as compared to the conventional SSF T/H stage. Moreover, the even harmonics are successfully suppressed using the differential topology, and the spurious-free dynamic range (SFDR) and total harmonic distortion (THD) are improved. To widen bandwidth (BW), the input and output buffers are designed using the distributed amplifier and source follower, respectively. With a sampling rate of 13.5 GS/s, the proposed THA features a measured 3-dB BW of 16 GHz, an SFDR of 46 dB, and a THD of −45 dB.

Highly Linear Distributed Mixer in 0.25- $\mu \text{m}$ Enhancement-Mode GaAs pHEMT Technology

This letter presents the design and measured results of novel wideband, highly linear gate-pumped distributed downconverter mixers. The circuit is realized in a 0.25-μm, Enhancement-mode GaAs pseudomorphic High Electron-Mobility Transistor process which requires no negative voltage supply. Two cells with different biases in parallel are used to achieve third-order intermodulation product cancelation. Each cell utilizes the distributed topology to absorb the first-order gate-source capacitances C gs1 . Two mixers are demonstrated: 1) a single-ended (SE) mixer and 2) a single-balanced (SB) mixer. The SE and SB mixers achieve a measured third-order input intercept point above 30 dBm in the RF frequency ranges from 6-26 GHz and 6-20 GHz, respectively. Both mixers show a conversion loss of less than 10 dB. The balanced mixer exhibits more than 30 dB of LO-RF isolation.

Transformer-Feedback Dual-Band Neutralization Technique

A dual-band neutralization technique based on the transformer feedback between the drain and the gate of a transistor is presented. The drain and gate bias lines of the transistor are realized as multiorder $LC$ networks. Transformer coupling between the inductors of the two networks can be used to concurrently neutralize the gate–drain capacitance of the transistor at multiple frequencies. Moreover, these frequencies can be placed close together to achieve wideband neutralization. A proof-of-concept dual-band 27/33-GHz amplifier is designed and implemented in a 0.1- $\mu\text{m}$ GaAs pseudomorphic high-electron mobility transistor process. The maximum gain of the transistor at the two frequency bands is improved by more than 6 dB using the neutralization technique. The amplifier exhibits a gain of 16/15 dB and a reverse isolation of 60/50 dB at the lower/upper frequency band. It consumes 24 mA from a 1-V supply.

A $K$ -Band High Efficiency High Power Monolithic GaAs Power Oscillator Using Class-E Network

This letter presents design of a K-band high power high efficiency monolithic GaAs power oscillators using class-E load network with finite dc-feed inductance. To further extend the operation frequency up to millimeter-wave band with high efficiency, the core transistor is operated in the saturated region with overdriven condition to obtain the bifurcated current waveform. The proposed power oscillator is fabricated using a 0.15- $\mu \text {m}$ GaAs pseudomorphic high-electron mobility transistor process, and it features a tuning range from 23.5 to 24.5 GHz, a peak efficiency of 19%, a maximum output power of 21 dBm, and a phase noise of −106.3 dBc/Hz at 1-MHz offset.

A 2.5 GHz High Efficiency High Power Low Phase Noise Monolithic Microwave Power Oscillator

This letter presents a 2.5 GHz high efficiency high power low phase noise monolithic microwave power oscillator using 0.5- $\mu{\rm m}$ GaAs enhancement- and depletion-mode pseudomorphic high-electron mobility transistor process. The class-E load network with finite dc-feed inductance is adopted in the power oscillators to achieve high efficiency. The shunt capacitance and load resistance of the class-E network can be larger than those of the class-E load network with the large dc-feed inductance. With a dc supply voltage of 4 V, the proposed power oscillator demonstrates a peak efficiency of 53%, a maximum output power of 24.8 dBm, and a minimum phase noise of $-$ 127 dBc/Hz at 1 MHz offset frequency.

A <formula formulatype="inline"><tex Notation="TeX">$W$</tex> </formula>-band High LO-to-RF Isolation Triple Cascode Mixer With Wide IF Bandwidth

A W-band triple cascode down conversion mixer using a 0.15- μm pseudomorphic high-electron mobility transistor process is proposed in this paper. Due to the utilization of modified bias topology, resistive mixing core, and IF low-pass filter, this circuit has a very wide IF bandwidth. Moreover, the triple cascode structure is used in this mixer for high local oscillator (LO)-to-RF isolation and compact chip area. The measured results illustrate that the mixer achieves 9-13-dB upper sideband conversion loss with dc-to-26-GHz IF bandwidth, and the LO-to-IF, LO-to-RF, and RF-to-IF isolation are 38, 42, and 40 dB, respectively with 5-dBm LO power at 86 GHz. When the LO power is 7 dBm at 96 GHz, the upper sideband conversion loss is 10-14 dB with dc-to-24-GHz IF bandwidth, and LO-to-IF, LO-to-RF, and RF-to-IF isolation are 29, 41.5, and 45 dB, respectively. The power consumption is 24 mW and chip area is 1 mm 2 .

Linear Doherty Power Amplifier With an Enhanced Back-Off Efficiency Mode for Handset Applications

This paper presents a linear Doherty power amplifier (PA) with enhanced back-off efficiency mode for handset applications. For linear Doherty operation, we analyze the gain modulation as well as the cancellation of the third-order intermodulation distortion in order to improve the linearity. A compact design method is also discussed to implement on a single chip for a handset. The proposed Doherty PA delivers good performance with regard to the third-generation (3G)/fourth-generation (4G) modulation signals. A switched-load power-mode PA is adopted in the proposed Doherty PA to enhance the efficiency in the low-power region with over 10-dB back-off. For demonstration purposes, the PA is implemented using an InGaP/GaAs heterojunction bipolar transistor and AlGaAs/InGaAs pseudomorphic high electron-mobility transistor process. The PA is tested at 1.85 GHz using both a long-term evolution signal with 16-quadrature amplitude modulation, 7.5-dB peak-to-average power ratio, and 10-MHz bandwidth (BW) and a wideband code division multiple access signal with 3.3-dB PAPR and 3.84-MHz BW. The proposed linear Doherty PA with an enhanced back-off efficiency mode delivers good performance in both the high- and low-power modes, implying that the dual-power-mode Doherty PA configuration can be a promising candidate for extending the battery life of handheld devices in 3G and 4G wireless communication systems.

A Dual Power-Mode Multi-Band Power Amplifier With Envelope Tracking for Handset Applications

This paper presents a dual power-mode and multi-band power amplifier (PA) for handset applications that improves the efficiency in low-power regions. This PA operates in two modes through path control by a shunt switched capacitor. The proposed control method provides efficient mode control without any efficiency degrading and bandwidth (BW) limiting. The proposed PA, in conjunction with a boosted supply modulator for envelope tracking (ET) operation not only in the high-power mode, but also in the low-power mode, delivers good performance at all average output power levels. The linearity is improved by ET through a proper envelope-shaping method. For demonstrative purposes, the PA and supply modulator are implemented using an InGaP/GaAs heterojunction bipolar transistor and AIGaAs/InGaAs enhancement/depletion-mode pseudomorphic high electron-mobility transistor process and a 0.18- $\mu$ m CMOS process, respectively. The ET PA is tested across the range of 1.7–2.0 GHz using a long-term evolution signal with 16 quadrature amplitude modulation, a 7.5-dB peak-to-average power ratio, and 10-MHz BW. The proposed dual power-mode multi-band ET PA delivers good performance for high- and low-power modes, indicating that the architecture is promising for handset PA applications.

A 50 MHz-1 GHz high linearity CATV amplifier with a 0.15 μm InGaAs PHEMT process

A 50 MHz-1 GHz low noise and high linearity amplifier monolithic-microwave integrated-circuit (MMIC) for cable TV is presented. A shunt AC voltage negative feedback combined with source current negative feedback is adopted to extend the bandwidth and linearity. A novel DC bias feedback is introduced to stabilize the operation point, which improved the linearity further. The circuit was fabricated with a 0.15 μm InGaAs PHEMT (pseudomorphic high electron mobility transistor) process. The test was carried out in 75 Ω systems from 50 MHz to 1 GHz. The measurement results showed that it gave a small signal gain of 16.5 dB with little gain ripples of less than ± 1 dB. An excellent noise figure of 1.7–2.9 dB is obtained in the designed band. The IIP3 is 16 dBm, which shows very good linearity. The CSO and CTB are high up to 68 dBc and 77 dBc, respectively. The chip area is 0.56 mm2 and the power dissipation is 110 mA with a 5 V supply. It is ideally suited to cable TV systems.

A 4 W K-band GaAs MMIC power amplifier with 22 dB gain

A 4 W K-band AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) monolithic microwave integrated circuit (MMIC) high power amplifier (PA) is reported. This amplifier is designed to fully match for a 50 Ω input and output impedance based on the 0.15 μm power PHEMT process. Under the condition of 5.6 V and 2.6 A DC bias, the amplifier has achieved a 22 dB small-signal gain, better than a 13 dB input return loss, and 36 dBm saturation power with 25% PAE from 19 to 22 GHz.

Hybrid rectenna and monolithic integrated zero-bias microwave rectifier

In this study, we have developed a hybrid sensitive rectenna (rectifier + antenna) system at 2.45 GHz. To achieve this system, we have first optimized and validated a zero-bias microwave sensitive rectifier using commercial Schottky diodes. We have then optimized and achieved a 2times2 patch antenna array, which is associated to the microwave rectifier in order to validate the rectenna system, where an RF-dc conversion efficiency of 56% has been observed experimentally. In order to minimize the rectenna dimensions, we have conducted a study using the OMMIC ED02AH 0.20-mum GaAs pseudomorphic high electron-mobility transistor process to develop and achieve a monolithic rectifier at 2.45 GHz with RF-dc conversion efficiency of 65%

High reliability in PHEMT MMICs with dual-etch-stop AlAs layers for high-speed RF switch applications

We have conducted a thorough investigation on the long-term process reliability for our recently developed dual-etch-stop (DES) pseudomorphic high electron mobility transistor (PHEMT) process using the on-wafer-level accelerated DC and RF biased step stress test up to 320 °C channel temperature as well as package-level three-temperature constant stress lifetest. Devices studied are 0.9-μm-gate InGaAs PHEMTs with two silicon-doped AlAs layers as gate and channel etch-stop materials. High-temperature-operating-life (HTOL) test on our single-pole-double-throw (SPDT) switch products using this DES PHEMT process has also been performed. This article describes the detailed reliability experiments and compares the reliability results of this new DES PHEMT process against the standard non-etch-stop (NES) PHEMT baseline material. Extensive statistical analyses on the DES PHEMT devices derived an activation energy E a=1.4 eV and a mean-time-to-failure (MTTF) > 10 7 h at 125 °C, an order of magnitude better than our baseline NES PHEMTs. This study demonstrates and discusses the excellent reliability in the DES PHEMT process for wireless communications applications.

AlGaAs/InGaAs Pseudomorphic High Electron Mobility Transistor using Pd/Ge Ohmic Contact

Microstructural reactions of a Pd/Ge contact to a AlGaAs/InGaAs pseudomorphic high electron mobility transistor (PHEMT) have been investigated, and the results have been used to interpret the changes of electrical properties of the PHEMT. In the as-deposited state, a ternary phase of PdxGaAs containing excess Ge atoms is formed at the interface of Pd/GaAs. When the ohmic metals deposited were annealed at 300°C, a PdGe compound was formed and its contact resistivity was decreased to 1.2×10-7 Ω·cm2. This is due to the preferential outdiffusion of Ga atoms to the PdGe during annealing, leaving Ga vacancies behind. Simultaneously, Ge atoms are indiffused to the GaAs and occupy the Ga vacancies, converting the interfacial GaAs layer into n+-GaAs. The low-temperature PdGe ohmic contact allows changing the sequence in the formation of source/drain and gate electrodes in the PHEMT process. The device performance was remarkably improved as the annealing temperature was increased or the contact resistivity was reduced. The PHEMTs with a gate length of 1.1 µm, annealed at 300°C, exhibit maximum transconductance of 381 mS/mm.