Pseudo Resistor Research Articles

An instrumentation amplifier with series switch pseudo resistor DC-servo loop realizing 0.16-Hz high-pass corner

This paper presents an instrumentation amplifier for electrocardiogram (ECG) signal recording. A DC servo loop (DSL) based on a series-switch pseudo resistor (S2PR ) is utilized to suppress the effect of the unavoidable electrode DC offset effectively. The two-step pulse generation circuit realizes two sets of pulse signals with shallow duty cycles, and the pulse signals drive the path switches and virtual switches in the S2PR, respectively. Virtual switches reduce the channel charge injection effect, and finally, a great equivalent resistance with high linearity is realized. The continuous DSL realized based on S2PR can suppress the electrode DC offset of ±180 mV. At the same time, the active area of the DSL is significantly reduced. The proposed instrumentation amplifier is realized in a standard 0.18-μm CMOS process. Simulation results show the DSL designed with a 1.8-V supply introduces a 0.16-Hz high-pass corner. The power consumption of the S2PR-DSL is 92.7 μW. The gain of the instrumentation amplifier is 39.8 dB, and the input-referred noise at the TT corner is 1.78 μVrms over a bandwidth of 0.5 Hz to 150 Hz. The input impedance of the instrumentation amplifier is 772.2 MΩ, when the input signal frequency is 50 Hz, and the total harmonic distortion (THD) of a 10-mVpp input sinusoidal signal at 9.033 Hz is −61.6 dB.

A pseudo resistor with temperature self-adaptive scheme

A temperature self-adaptive ultra-high-resistance pseudo-resistor (PR) circuit is proposed for a wide range of biomedical applications. It acts as a relatively constant resistor over a wide temperature range (−40 °C–85 °C) due to its potential to compensate for the impact of the temperature-induced current. Hence, the performance of many biomedical analog intellectual property (IP) circuits can be effectively improved with temperature variations. The proposed circuit consists of a gate-voltage-controlled pseudo-resistor and a proportional-to- absolute-temperature (PTAT) circuit. Besides, its analysis and proof of concept with the self-adaptive scheme are presented. The circuit is designed in standard 0.18 μm CMOS technology and occupies a silicon area of 18.5 × 43.7 μm2. It consumes 12 nW with a single power supply of 1.8 V. The post-layout simulation results demonstrate that the proposed pseudo-resistor could adequately improve the temperature-induced resistance variation by up to 18X while consuming ultra-low power and providing relatively high-temperature independence compared to the prior art.

A chopper amplifier with a pseudo MOS resistor-based tunable bandwidth for EEG applications

PurposeThe purpose of chopper amplifier is to provide the wideband frequency to support biomedical signals.Design/methodology/approachThis paper proposes a chopper-stabilized amplifier with a cascoded operational transconductance amplifier. The high impedance loop is established using an MOS pseudo resistor and with a tunable MOS capacitor.FindingsThe total power consumption is 451 nW with a supplied voltage of 800 mV. The Gain and common mode rejection ratio are 48 dB and 78 dB, respectively.Research limitations/implicationsAll kinds of real time data analysis was not carried out, only few test samples related to EEG signals are validated because the real time chip was not manufactured due to funding issues.Practical implicationsThe proposed work was validated with Monte-Carlo simulations. There is no external funding for the proposed work. So there is no fabrication for the design. But post simulations are performed.Originality/valueThe high impedance loop is established using an MOS pseudo resistor and with a tunable MOS capacitor. To the best of the author’s knowledge, this concept is completely novel and there are no publications on this work. All the modules designed for chopper amplifier are new concepts.

A compact sub-Hertz local field potential amplifier for implantable biomedical devices

Local field potentials (LFPs) are the ensemble of low frequency neural signals recorded invasively via microelectrodes implanted into brain tissues. The LFP signals acquired by micro-electrodes are very small in amplitude, typically in the range of 1 μV to 0.5 mV, depending on the distance from the electrode and on the size of a cell and contain the signal energy below 1 Hz. These weak signals are required to be amplified by an analog front-end amplifier. In this paper, the design methodology of a local field potential amplifier for an implantable neural recording system is presented. The LFP amplifier is implemented through a low power, low noise front-end instrumentation amplifier. In order to suppress large electrode-induced DC offset voltages, a modified pseudo-resistor is employed in the amplifier’s feedback. The enlarged resistance offered by the pseudo resistor realizes a high-pass cut-off frequency which is well suited for capturing the neural signals occurring in the sub-Hertz frequency range. As a case study, the instrumentation amplifier featuring modified pseudo resistor configured for LFP recording applications is fabricated in a standard 0.18μm CMOS process technology. The measurement results show the proposed LFP amplifier has a low-pass corner frequency of 300 Hz and achieves a high-pass corner frequency of 0.009 Hz with a maximum gain of 37 dB. The LFP circuit fully integrated on-chip occupies an active area of 0.056 mm2 and a power consumption of 1.8 μW from a 1.5-V supply.

A Bootstrapped Pseudo Resistor by Reusing OTA-C Filter for Neural Signal Processing

In integrated neural signal monitoring systems, pseudo resistor (PR) is widely used to form very large time constant filters, due to its large impedance within an acceptable die area. However, its linearity (the dependency of the resistance to applied voltage) and impedance are limited by the nonlinear MOS transistors in weak inversion, and suffers from process, voltage and temperature (PVT) variations. In this brief, a PR bootstrapped by reusing the operational transconductance amplifier-capacitor (OTA-C) filter is presented, it substantially increases the impedance and linearity to dynamically support lower frequency neural signal applications. It has no need for extra bias scheme on the gate or bulk, which decreases the circuit complexity, die area and power consumption. The proposed circuit implemented in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process occupies an area of 0.026 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the impedance of the bootstrapped PR is approximately 94 G <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> , and the high-pass cut-off frequency is reduced to 0.5 mHz.

Temperature-insensitive Pseudo-resistor

A novel pseudo-resistor insensitive to temperature change is proposed. In order for the pseudo-resistor implemented in the previous capacitively coupled instrumentation amplifier (CCIA) or transimpedance amplifier (TIA) to be used in the industrial temperature range (-40 ℃ to 85 ℃), it is necessary to develop a pseudo resistor insensitive to temperature change. The new pseudo-resistor can adjust the resistance value and the temperature sensitivity can be tuned. The pseudo-resistor is implemented using two PMOSs connected in series and a gate bias control block. A current proportional to the absolute temperature is used to control the magnitude of the pseudo-resistance and its temperature sensitivity. It was designed and laid out based on the 0.18 μm CMOS process, and as a result of simulation, it was possible to adjust the resistance value between 1.7 GΩ and 10.4 GΩ. The temperature sensitivity of the pseudo-resistor was able to obtain a minimum value of 91 ppm/℃ in the range of -40 ℃ to 85 ℃.

A front-end amplifier with tunable bandwidth and high value pseudo resistor for neural recording implants

In this paper, a tunable front-end amplifier is presented for neural recording implants. To program the low cut-off frequency, a bias circuit is used to adjust the value of pseudo resistors with lower sensitivity to the process variations and also to achieve very large value about 1 TΩ with high linearity. The band pass filter (BPF) can adjust high cut-off frequency and power consumption with two recording modes. The high cut-off frequency is 4.15 kHz and 8.2 kHz in low recording (LR) and high recording (HR) modes, respectively. The low cut-off frequency can be adjusted to 0.8 Hz and 300 Hz. The proposed amplifier is able to separate the neural signals with different frequencies for amplification. It has been designed and simulated in TSMC 0.18 μm CMOS process. The achieved input-referred noise is about 2.1 μVrms and 1.7 μVrms in HR and LR modes, respectively. The total power consumption is 3.6 μW from a 1-V supply with −46.3 dB THD.

A Bio-IA With Fast Recovery and Constant Bandwidth for Wearable Bio-Sensors

This paper proposes a bio-signal instrumentation amplifier (Bio-IA) with fast recovery and constant bandwidth for wearable bio-sensors. To shorten the offset calibration time of the Bio-IA and reduce the loss of bio-signal in the calibration process, a digital-controlled DC servo loop (DCDSL) with fast recovery is designed, which achieves a larger offset calibration range and a faster calibration speed. The proposed programmable gain amplifier (PGA) with constant bandwidth uses dual-biased pseudo-resistor (PR) to stabilize the passband width under different gains, effectively preventing the loss of low-frequency signals. Besides, this paper analyzes the noise of the DCDSL and the noise of dual-biased PR for the first time. The presented Bio-IA was implemented in a 0.18- μm CMOS process, occupying a core area of 849 μm×451 μm. The measured results show that the Bio-IA can calibrate a DC offset of ±511 mV, and the response time is less than 70 ms when the offset polarity changes suddenly. When the gain of the Bio-IA varies from 26 to 40 dB, its passband width remains constant, and the high-pass and low-pass cut-off frequencies are 0.4 Hz and 200 Hz, respectively. The input-referred noise over the range of 0.1-200 Hz is 0.72 μVrms. The proposed Bio-IA consumes 5.5 μW from 1.2 V supply voltage.

Process voltage temperature analysis of MOS based balanced pseudo-resistors for biomedical analog circuit applications

PurposeAdoption of integrated MOS based pseudo-resistor (PR) structures instead of using off-chip passive poly resistors for analog circuits in complementary metal oxide semiconductor technology (CMOS) is an area-efficient way for realizing larger time constants. However, issue of common-mode voltage shifting and excess dependency on the process and temperature variations introduce nonlinearity in such structures. So there is dire need to not only closely look for the origin of the problem with the help of a thorough mathematical analysis but also suggest the most suitable PR structure for the purpose catering broadly to biomedical analog circuit applications.Design/methodology/approachIn this work, incremental resistance (IR) expressions and IR range for balanced PR (BPR) structures operating in the subthreshold region have been closely analyzed for broader range of process-voltage-temperature variations. All the post-layout simulations have been obtained using BSIM3V3 device models in 0.18 µm standard CMOS process.FindingsThe obtained results show that the pertinent problem of common-mode voltage shifting in such PR structures is completely resolved in scaled gate linearization and bulk-driven quasi-floating gate (BDQFG) BPR structures. Among all BPR structures, BDQFG BPR remarkably shows constant IR value of 1 TΩ over −1 V to 1 V voltage swing for wider process and temperature variations.Research limitations/implicationsVarious balanced PR design techniques reported in this work will help the research community in implementing larger time constants for analog-mixed signal circuits.Social implicationsThe PR design techniques presented in the present piece of work is expected to be used in developing tunable and accurate biomedical prosthetics.Originality/valueThe BPR structures thoroughly analyzed and reported in this work may be useful in the design of analog circuits specifically for applications such as neural signal recording, cardiac electrical impedance tomography and other low-frequency biomedical applications.

Design of low power, programmable low-Gm OTAs and Gm-C filters for biomedical applications

In this paper, two programmable operational transconductance amplifiers (POTAs)—one using bulk driven attenuator (BDA) and another using programmable current mirror (PCM) are proposed in order to achieve low-Gm and high dynamic range. These OTAs are denoted as BDA-POTA and PCM-OTA respectively and are realized using composite transistors operated in the subthreshold region. The pseudo resistor is used for achieving programmability in the former and for improving the linearity and dynamic range in the latter. The proposed OTAs and two 4th order programmable Butterworth low pass filters (LPF) are designed and implemented in CMOS 180 nm technology with a supply voltage of 0.9 V. Their performances are evaluated through post-layout simulations and are found to be superior compared to those of POTAs reported in the literature for biomedical applications. The power consumption, transconductance, dynamic range and input-referred noise of BDA-POTA and PCM-OTA are [25.2 nW, (7.89–15.61 nS), (77.54–74.89 dB), (39.86–51.19 µVrms)] and [72.81 nW, (5.49–174.5 nS), (91.20–84.39 dB), (17.19–34.92 µVrms)] respectively. The power dissipation and cut off frequency range of the LPF using BDA-POTA and PCM-OTA are [197.8 nW, (30–100 Hz)] and [209.8 nW, (16–971 Hz)] respectively. The latter achieves 13.6 times wider programmability with only 5% increase in power dissipation. The proposed LPFs have better FOM compared to those reported in the literature.

MOS based pseudo-resistors exhibiting Tera Ohms of Incremental Resistance for biomedical applications: Analysis and proof of concept

Performance of biomedical analog circuits vitiates due to non-linear V-R characteristics of Pseudo-resistor (PR) structure, their excess dependency over Process Voltage Temperature (PVT) and common mode variations. In this paper, Incremental Resistance (IR) expressions, V-R curves and statistical results for wider PVT variations for diverse categories of non-tunable and tunable PR structures have been presented. The results obtained using 0.18 μm standard CMOS process with BSIM3V3 device models show that Dynamic Threshold Metal Oxide Semiconductor (DTMOS) technique involving symmetrical biasing for bulk and gate voltages for MOS devices is capable to emulate high nominal value (RYX, N) of IR of the order of 1.95 TΩ over a wider voltage swing of −1 V to 1 V with an area consumption of 60 μm2. Statistical results obtained after performing Monte Carlo Simulations (MCS) with 100 runs for the verification of robustness against PVT variations for this structure shows the value of mean (μ), standard deviation (σ) and Coefficient of variance (CV = σ/μ) as 1.918 TΩ, 100.6 GΩ and 0.052 respectively. Results for a variety of other PR structures reported in this paper can be useful for their possible deployment in circuit applications like neural signal recording and low current sensing etc.

Design and simulation of pseudo-resistor with extremely high linearity for an improved neural signal recording.

Design of a pseudo-resistor (PR) structure based on a bulk driven quasi floating technique is presented, which not only provides a high value of resistance (≈1 TΩ) over a wider voltage swing of -1 V to 1 V, but also displays extremely high linearity. The same is useful for accurate amplification and recording of neural signals for better diagnosis of many chronic diseases. PR design reported in this paper has been simulated in 0.18 µm technology with BSIM3V3 MOS device models in the 6M1P standard process. The proposed PR has been simulated for its accuracy through its use in the design of the neural amplifier with a display of better performance than earlier reported work.

Temperature effect and compensation scheme for tunable ultra-high-resistance pseudo resistor

Pseudo resistors with ultra-high resistance implemented using MOSFETS are employed in a wide range of biomedical applications. However, their resistances are highly dependent on temperature. A gate-voltage-controlled pseudo resistor is proposed to compensate the temperature impact through trimming. Simplified models have been proposed for analyzing the pseudo resistor, and a linear trimming scheme is proposed. The proposed tunable pseudo resistor is fabricated and measured in standard 0.35 μm CMOS technology. Experimental results demonstrated that tuning could adequately compensate the temperature-induced resistance variation by 8.75x and provide relatively low-temperature dependence.

Feedback controlled pseudo resistor

The pseudo resistor (PR) is widely used in integrated circuits. It comprises two transistors back-to-back to force them into the sub-threshold region, which provides large resistance with a small die area. However, its linearity is limited by the non-linear MOS transistors in weak inversion. In this Letter, a new PR topology is proposed, employing a feedback loop that continuously adjusts the voltage at the shared gate node of the PR with the input signal. The proposed architecture substantially increases the linearity and impedance of the PR.

A novel programmable attenuator based low Gm-OTA for biomedical applications

In this paper, a novel programmable operational transconductance amplifier (POTA) using a pseudo resistor based programmable attenuator is proposed. A 4th order Butterworth programmable low pass filter (LPF) targeted for biomedical applications is designed using the proposed POTA. The proposed POTA and the LPF are designed and implemented in 0.18 ​μm CMOS technology with a supply voltage of 1 ​V and their performances are evaluated through post-layout simulations. The proposed POTA consumes a power of 27 ​nW, and its transconductance could be varied from 27 ​nA/V to 75 ​nA/V. It has higher linearity, dynamic range (DR) of 85.62 ​dB–79.46 ​dB and lower input-referred noise (IRN) of 33.15 μVrms to 58.65 μVrms than pre-input voltage attenuator based OTAs. The proposed LPF consumes a power of 208 ​nW. Its output dynamic range and IM3 lie in the range of (62.1 ​dB–49.26 ​dB) and (61.87 ​dB–53.14 ​dB) respectively. Its cutoff frequency can be varied from 100 ​Hz to 250 ​Hz.

Vital-Sign Processing Receiver With Clutter Elimination Using Servo Feedback Loop for UWB Pulse Radar System

This brief presents a vital-sign processing circuit for simultaneous dc/near-dc elimination and out-of-band interference rejection without any digital signal processing or algorithm assistance for the ultrawideband (UWB) pulse-based radar system. An intrinsic self-balanced MOS diode (SBMD) was proposed as a stable and balanced pseudo resistor applied under a servo feedback loop in a vital-sign receiver of the sensing radar to perform as a high-pass filter (HPF) with an ultralow corner frequency lower than 0.5 Hz for removing undesired clutters of the reflected signals and input dc-offset voltages from innate circuit offsets. A third-order switched-capacitor (SC) Chebyshev low-pass filter (LPF) with leap-frog topology as the subsequent stage was adopted to suppress the out-band noises, thereby establishing an integrated vital-sign processing circuit with bandpass frequency response and incorporating it into a radar module to verify its viability.

A Robust Bio-IA With Digitally Controlled DC-Servo Loop and Improved Pseudo-Resistor

Bio-signal instrumentation amplifier (Bio-IA) is one of the most important circuit in the vital sign monitoring system. However, the performance of the Bio-IA using traditional pseudo-resistor (PR) is always very sensitive to process, power voltage and temperature (PVT). This brief proposed a digitally controlled dc-servo loop (DCDSL) and an improved PR to improve the robustness of Bio-IA. The proposed DCDSL replaces the integrator-based DSL and eliminates the PR in the traditional DSL, which can improve the response speed as well as the noise performance. The presented Bio-IA was implemented in a standard 0.18 $\mu \text{m}$ CMOS process, occupying an active area of $0.474\times 0.424$ mm2. The measured results shows that the Bio-IA can operate in the temperature range of −20°C~80°C. When the bias current is 500 fA, the equivalent resistance of the improved PR can be up to 330 $\text{G}{\boldsymbol{\Omega }}$ . The proposed Bio-IA can calibrate the dc offset as large as ±300 mV with a response time less than 200 ms. When the dc offset increases from 0 to 300 mV, its input-referred noise varies from 0.67 $\mu $ Vrms to 1.49 $\mu $ Vrms. With 1.2 V supply voltage, the midband gain of the Bio-IA is 40 dB.

A Forward-Body-Bias CMOS LNA With Ultra-Low Device Junction Leakage Using Intrinsic Self-Balanced Pseudo Resistor

A fully differential LNA with forward-body-bias (FBB) technique using an intrinsic self-balanced MOSFET is presented in this brief for low-impact device junction leakage and process, voltage, and temperature (PVT) variations. A proposed natural back-to-back connected diode directly from the source-bulk and bulk-drain junctions of a MOSFET performs as a stable and balanced pseudo resistor for minimizing leakage current at the transconductance stage of a FBB LNA. In addition, the FBB voltage is injected into the bulk of the MOSFET to allow a full-swing operation, in particular simultaneously at a gate-driven and body-driven input stage. In comparison to the conventional topologies of pseudo resistor, the simulated and measured results show that the proposed FBB technique applied at the LNA with the dual cross coupling configuration can indeed extend the overall dynamic range of the pseudo resistor and relief PVT variations under the same extreme condition, with a larger forward bias voltage close to the breakdown leakage current transition corner of the P-N junction.

14.85 µW Analog Front-End for Photoplethysmography Acquisition with 142-dBΩ Gain and 64.2-pArms Noise.

A low-power, high-gain, and low-noise analog front-end (AFE) for wearable photoplethysmography (PPG) acquisition systems is designed and fabricated in a 0.35 μm CMOS process. A high transimpedance gain of 142 dBΩ and a low input-referred noise of only 64.2 pArms was achieved. A Sub-Hz filter was integrated using a pseudo resistor, resulting in a small silicon area. To mitigate the saturation problem caused by background light (BGL), a BGL cancellation loop and a new simple automatic gain control block are used to enhance the dynamic range and improve the linearity of the AFE. The measurement results show that a DC photocurrent component up-to-10 μA can be rejected and the PPG output swing can reach 1.42 Vpp at THD < 1%. The chip consumes a total power of 14.85 μW using a single 3.3-V power supply. In this work, the small area and efficiently integrated blocks were used to implement the PPG AFE and the silicon area is minimized to 0.8 mm × 0.8 mm.

An Integrated Approach of CNT Front-end Amplifier towards Spikes Monitoring for Neuro-prosthetic Diagnosis

The future neuro-prosthetic devices would be required spikes data monitoring through sub-nanoscale transistors that enables to neuroscientists and clinicals for scalable, wireless and implantable applications. This research investigates the spikes monitoring through integrated CNT front-end amplifier for neuro-prosthetic diagnosis. The proposed carbon nanotube-based architecture consists of front-end amplifier (FEA), integrate fire neuron and pseudo resistor technique that observed high electrical performance through neural activity. A pseudo resistor technique ensures large input impedance for integrated FEA by compensating the input leakage current. While carbon nanotube based FEA provides low-voltage operation with directly impacts on the power consumption and also give detector size that demonstrates fidelity of the neural signals. The observed neural activity shows amplitude of spiking in terms of action potential up to 80 μV while local field potentials up to 40 mV by using proposed architecture. This fully integrated architecture is implemented in Analog cadence virtuoso using design kit of CNT process. The fabricated chip consumes less power consumption of 2 μW under the supply voltage of 0.7 V. The experimental and simulated results of the integrated FEA achieves 60 GΩ of input impedance and input referred noise of 8.5 nv/ $$\rm\sqrt{Hz}$$ over the wide bandwidth. Moreover, measured gain of the amplifier achieves 75 dB midband from range of 1 KHz to 35 KHz. The proposed research provides refreshing neural recording data through nanotube integrated circuit and which could be beneficial for the next generation neuroscientists.