Pseudo-random Bit Sequence Generator Research Articles

The influence of electrical filters with sequence generators on optical ISL performance evolution with suitable data rates

Abstract The work offered the analysis comparison study of optical wireless intersatellite link (ISL) for both different bit sequence generators and filters. The study clarifies the impact of varying sorts of both bit sequence generator (data source) in the transmitter and electrical filters in receiver on system performance. The two bit sequence generators used are pseudo random bit sequence generator (PRBSG) and user-defined bit sequence generator (UDBSG). The used filters in this study are low pass (LP) Bessel filter, LP Gaussian filter, LPCROF (cosine roll-off filter), and LPSCROF (squared CROF). Performance of the filter depends on the order of filter and filter bandwidth. The performance parameters in our study are quality factor, Bit Error Rate (BER), and optical received power. In this study, variation of optical received power depends on the type of sequence generator because it is measured after the channel directly.

A 2–18 GHz Compressed Sensing Receiver With Broadband LO Chain in 0.13-$\mu$ m BiCMOS

We present an integrated 2–18 GHz four-channel compressed sensing receiver (CSRX), which performs a $128.5\times $ sub-Nyquist acquisition with 36-Gb/s pseudorandom bit sequence (PRBS) generators in 0.13- $\mu \text{m}$ BiCMOS. The integrated four-channel CSRX consists of broadband receiver chains, each of which includes a distributed RF buffer that operates as an active balun at 2–18 GHz, followed by a double-balanced passive mixer for high local-oscillator (LO)-to-intermediate frequency (IF) isolation at the IF band, and a 700-MHz variable gain amplifier (VGA). Four independent 36-Gb/s PRBS generators are integrated to perform the compressed sensing by mixing the PRBS signal as the random modulator. To deliver the generated wideband PRBS signal to the mixer, the LO driver conducts band-equalization by applying a shunt-shunt feedback amplifier to compensate for the high-frequency degradation of the PRBS LO tones through the LO generation stage. The chip consumes 195 mA per channel with a 2.5-V supply.

A 0.87-pJ/b 115-Gb/s $2^{\text {7}}$ -1 PRBS Generator in 130-nm SiGe:C BiCMOS Technology

A $2^{{7}}$ -1 pseudo-random bit sequence (PRBS) generator, implemented in a 130-nm SiGe:C BiCMOS technology with $\text{f}_{\text {T}}/\text{f}_{\text {max}}$ of 300/500 GHz, is presented. The generator uses a modified half-rate clock topology which enables it to operate at data rates up to 115 Gb/s with low power consumption. Time-domain measurements are performed to demonstrate the maximum data rate of the circuit, which delivers a differential output voltage swing of 600 mVpp and dissipates 700 mW. Spectrum measurements are also carried out to validate the generated PRBS sequence. To the best knowledge of the authors, this is the first time a PRBS generator achieves such data rate with a record efficiency of 0.87 pJ/b.

A Versatile 10–80-Gb/s PRBS-Based Broadband Transmitter With Arbitrary 20–60-GHz Spectrum Shifting

A versatile pseudorandom bit sequence (PRBS)-based transmitter with the ability to mix the generated PRBS spectrum to arbitrary frequencies is presented. It incorporates a $2^{11} -1$ 80-Gb/s PRBS generator, employing parallel architecture. The generator is optimized to provide a high bit rate as well as a long sequence length for low power consumption without any need of inductive peaking, compared with the PRBS generators reported in the literature. The PRBS generator is capable of generating bit rates ranging from 10 up to 80 Gb/s. The transmitter can shift the generated PRBS spectrum to arbitrary frequencies ranging from 20 to 60 GHz via a broadband mixer of a double sideband output spectrum of 80-GHz bandwidth. A radar is realized using the presented transmitter, where a range resolution of 7.5 mm could be achieved. The transmitter consumes power ranging from 576 mW to 1 W, depending on the output bit rate of the integrated PRBS generator. The proposed circuit was manufactured in an 0.35- $\mu \text{m}$ SiGe technology with an $f_{t}$ of 200 GHz.

Monolithic ultra‐low‐power 6 Gbit/s inductorless PRBS generator for silicon HBT‐based carrier‐injection electro‐absorption modulator

A low-power pseudo-random bit sequence (PRBS) generator for testing a high-speed optical transmitter module has been realised in a 130 nm bipolar CMOS process. The transmitter consists of a monolithic driver circuit architecture and a heterojunction bipolar transistor (HBT)-based carrier-injection electro-absorption modulator. A 10 Gbit/s current mode logic latch with only 0.6 mW power consumption is designed by scaling down the current density without degrading the overall transmitter speed performance. The 27−1 PRBS generator circuit consumes only 42.75 mW at 6 Gbit/s operating speeds with a 1.5 V dc power supply. The core circuit power consumption is 9 mW.

A 3$\,\times\,$5-Gb/s Multilane Low-Power 0.18-$\mu{\hbox {m}}$ CMOS Pseudorandom Bit Sequence Generator

A low-power, three-lane, pseudorandom bit sequence (PRBS) generator has been fabricated in a 0.18-mum CMOS process to test a multilane multi-Gb/s transmitter that cancels far-end crosstalk. Although the proposed PRBS generator was designed to produce three uncorrelated 12-Gb/s PRBS sequences, measurement results included in this paper have been obtained at only 5 Gb/s due to test setup limitations. The prototype employs a CMOS latch optimized to operate at frequencies close to the of the process and a current-mode logic (CML) MUX with modified active inductor loads for better high-speed large-signal behavior. In order to reduce the power consumption, a quarter-clock rate linear feedback shift register (LFSR) core in a power-efficient parallel architecture has been implemented to minimize the use of power-hungry, high-speed circuitry. Further power reduction has been achieved through the clever partitioning of the system into static logic and CML. In addition, the prototype design produces three uncorrelated 12-Gb/s data streams from a single quarter-rate LFSR core, thereby amortizing the power across multiple channels which lowers the power per channel by 3 times. The total measured power consumption at 5 Gb/s is 131 mW per lane and the calculated figure of merit per lane is 0.84 pJ/bit, which is significantly better than previously published designs.

100-Gb/s 2/sup 7/-1 and 54-Gb/s 2/sup 11/-1 PRBS generators in SiGe bipolar technology

This paper presents two monolithic pseudorandom bit sequence (PRBS) generators. One circuit uses a seven-stage shift register operating with a half-rate clock and provides output signals up to 100 Gb/s. The second circuit contains an eleven-stage shift register operating with a full-rate clock up to 54 Gb/s. Both PRBS generators provide a wide range of data rates down to below 1 Gb/s simply by changing the frequency of the external clock signal without the need of any further adjustments. The integrated circuits provide a trigger output which can be switched between eye and pattern display. Furthermore, they contain additional circuitry to guarantee automatic start after power-on. The circuits are manufactured in a 200-GHz f/sub T/ SiGe bipolar technology. They each have a chip size of 900/spl times/700 /spl mu/m/sup 2/ and consume 1.5 and 1.9 W, respectively.

High-speed demonstration of a superconducting pseudo-random bit-sequence generator

This paper describes the design, analysis and test results for a 4-bit pseudo-random bit-sequence generator (PRBSG) implemented with complementary output switching logic (COSL) gates. The PRBSG was optimized using a Monte Carlo simulation method for 10-GHz operation. The circuit has been fabricated using niobium technology with critical current density of 1 kA/cm/sup 2/ and sheet resistance of 1 /spl Omega//sq. The 4-bit PRBSG consists of 12 gates and its area is 1530/spl times/950 /spl mu/m/sup 2/. It has been fully tested with a three-phase power supply, and its power consumption is 0.15 mW. The correct operations have been verified experimentally at clock frequencies of up to 2 GHz.