Pseudo-differential Structure Research Articles

A Pseudo-Differential LNA with Noise Improvement Techniques for Concurrent Multi-Band GNSS Applications

A low-noise amplifier (LNA) design with the operation of concurrent dual-band for Global Navigation Satellite System (GNSS) receivers with single channel is presented in this work. This LNA structure has an inductively degenerated cascode architecture and is pseudo-differential, operating at two frequencies simultaneously (1.2 GHz and 1.57 GHz). Two noise reduction/cancellation techniques, using load capacitor and feedforward path, respectively, are proposed resulting in an excellent improvement in the noise figure (NF). The input matching circuit uses both series and parallel resonant components to enable concurrency. The adopted pseudo-differential structure results in input balun elimination. Inductively degenerated cascode topology provides both input impedance and optimum noise impedance matching. The soundness of the proposed approach has been demonstrated in a 0.18-µm CMOS technology by TSMC. Simulation results show that at 1.2 GHz and 1.57 GHz the LNA achieves −13 dB and −11 dB of input matching, 24.6 dB and 24.7 dB of gain, 1.47 dB and 1.43 dB of NF, respectively. The input-referred 1-dB compression point (IP1dB) is around −16 dBm, while the input-referred third-order intercept point (IIP3) achieves −2.2 dBm at 1.2 GHz and −0.6 dBm at 1.57 GHz. The LNA draws about 13 mA from a 1.8-V supply voltage.

A Wideband Power Amplifier in 65 nm CMOS Covering 25.8 GHz–36.9 GHz by Staggering Tuned MCRs

Broadband millimeter-wave power amplifiers have attracted much attention and have wide applications for 5G communication, satellite communication, radar, sensing, etc. Yet, it is challenging to design a power amplifier with broadband small-signal gain and power performance simultaneously. In this study, a transformer-based symmetrical magnetically coupled resonator (MCR) matching network for broadband output matching and stagger-tuned MCRs are used to achieve both broadband small- and large-signal performance. Also, to enhance the gain for the power amplifier, a three-stage common-source pseudo-differential structure is adopted to mitigate the low-gain issue due to stagger tuning, and the shunt resistors aimed to decrease the Q factor of the MCRs. We used the in-phase two-way current combined with microstrip transmission lines to increase the output power. Designed in 65 nm bulky CMOS technology, the power amplifier presents a 3 dB small-signal gain bandwidth from 25.8 GHz to 36.9 GHz, indicating a peak gain of 25.87 dB at 30.5 GHz. The power amplifier demonstrates a 17.84 dBm saturated output power (Psat) at 31 GHz and a 24.37% peak power added efficiency (PAEmax) at 28 GHz. The power amplifier achieves a flat Psat of 17.44 ± 0.4 dBm, a PAEmax of 22.59 ± 1.78%, and an OP1dB of 13.78 ± 0.31 dBm from 26 GHz to 36 GHz.

A 28-GHz wideband power amplifier with dual-pole tuning superposition technique in 55-nm RF CMOS

This paper presents a 28-GHz wideband power amplifier (PA) with the dual-pole tuning superposition technique for 5G applications in a 55-nm RF CMOS. The PA employs a four-stage pseudo-differential structure together with the two-way combining approach to enhance the power gain. Transmission-line transformer (TLT) matching networks are proposed in the PA for not only performing the impedance matching, but also tuning the peak gains of the four stages to two different pole frequencies. The dual-pole frequencies are eventually superposed to improve the bandwidth and gain. Meanwhile, techniques of capacitance neutralization, load-pulling, and power combination are adopted for power stages to improve the output power and efficiency significantly. Biased at the class-A mode by a supply voltage VDD of 1.5 V, the fabricated PA exhibites the measured peak small-signal gain (S21) of 21.9 dB and power gain (PG) of 20 dB at 28 GHz. The measured performances of saturated output power (Psat) of 15.4–16.8 dBm, output 1-dB compression point (OP1dB) of 12–13.5 dBm, and power added efficiency (PAEP1dB) of 11%–14.7% are achieved over the bandwidth of 24–30 GHz, featuring wideband linearity/PAE. The chip occupies a core area of 1.5 × 0.6 mm2.

Compact CMOS Wideband Instrumentation Amplifiers for Multi-Frequency Bioimpedance Measurement: A Design Procedure

The design of an instrumentation amplifier (IA), based on indirect current feedback and suited to electrical bioimpedance spectroscopy, is presented. The IA consists of two transconductors and a summing stage, featuring a single-stage configuration process that allows the maximum achievable bandwidth to be extended. The transconductors are linearized by means of resistive source degeneration, whereas the use of super source followers allows a reduction in the values of the source degeneration resistors. This fact leads to a decrease in the overall noise and the silicon area, thus resulting in a compact implementation. A thorough analysis of the proposed solution, accompanied by a design procedure and verified by means of electrical simulations, is also provided. Two versions of the IA, i.e., a single-ended (SE) and a pseudo-differential (PD) structure, were designed and fabricated using 180 nm CMOS technology to operate with a 1.8 V supply. The experimental results, including a BW of 5.2 MHz/8.0 MHz, a CMRR higher than 72 dB/80 dB, a DC current consumption of 139.0 μA/219.3 μA and a silicon area equal to 0.0173 mm2/0.0291 mm2 for the SE/PD implementation, validate the suitability of the approach.

Origins and minimization of intermodulation distortion in a pseudo-differential CMOS beamforming receiver

This paper studies how nonlinear distortion is generated in the combination of an inverter-based low-noise amplifier and a passive mixer. The dominant nonlinearity appears to be the quadratic V_{gs}V_{ds} mixing term in the passive mixer that first causes low-frequency IM2 and then upconverts it to IM3. Adding a common-mode feedback (CMFB) cancels the IM2 in a pseudo-differential structure, and hence also reduces the IM3 caused by the cascaded second order nonlinearities significantly. The effect of CMFB gain, bandwidth and linearity were analyzed, and it is concluded that from the linearity point of view, the feedback circuit does not have to be very wideband since the dominant distortion products originate from baseband. Finally, the paper takes a look at the spurious tones rising in the mixing, and how to extend the analysis to include the actual frequency translation effect.

A Low Noise 28Gbaud/s Linear PAM4 Receiver Front-End for Optical Communication Applications in 0.13μm BiCMOS Technology

This paper presents a low noise 28 Gbaud/s linear receiver front-end for fourth-order pulse amplitude modulation (PAM4) signal applied in the field of optical communication. The designed receiver front-end includes a transimpedance amplifier(TIA), an automatic gain control (AGC) and a DC offset cancellation (DCOC) circuit. The pseudo-differential structure of the TIA is designed to achieve low noise. The resistance and capacitance degradation technology are introduced in the variable gain amplifier(VGA) and the equalizer(EQ) to improve linearity and optimize the bandwidth. In the AGC mode, the feedback loop controls the output amplitude to be a desired value within a large range of input current. The PAM4 optical receiver front-end achieves a maximum differential transimpedance gain of 76 dBΩ and -3dB bandwidth of 27 GHz. The equivalent input noise current density with the front-end circuit is . In 0.13µm BiCMOS technology, the PAM4 front-end chip consumes 200 mW with a 3.3V voltage supply.

A 25-Gb/s inductorless SiGe BiCMOS receiver for 100-Gb/s optical links

This paper presents the design and measurements of a 25-Gb/s inductorless optical receiver in a 0.25-μm SiGe BiCMOS process for 100-Gb/s (25-Gb/s × 4 lines) Ethernet. As the first stage of the proposed optical receiver, a transimpedance amplifier (TIA) employing a pseudo-differential structure with a feedback resistor incorporates DC offset cancellation (DOC) to enhance the input dynamic range. Cascaded by the improved two-stage limiting amplifiers and a 50-Ω output buffer, the receiver achieves high differential swings. For a bit-error rate (BER) of 10−12 at 25 Gb/s, the measured transimpedance gain, bandwidth, sensitivity, and output swing are 63.17 dBΩ, 20.7 GHz, −10.3 dBm, and 352.7 mV, respectively. The power consumption of the entire receiver is 111.6 mW and the core area of the die is 640 μm × 135 μm.

High Input Impedance Low-Noise CMOS Analog Frontend IC for Wearable Electrocardiogram Monitoring

This brief presents a CMOS analog frontend (AFE) IC with high input impedance low input-referred noise, which for wearable electrocardiogram monitoring. The IC has three main parts, pseudo-differential chopper-stabilized instrumentation amplifier, switched capacitor filter, and low-power continuous–time <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${{\Sigma}} {{\Delta }}$ </tex-math></inline-formula> modulator. The pseudo-differential structure with chopper stabilization improves the input impedance, input–referred noise and chip area. Notably, we propose a new type of negative capacitor circuit to further boost the input impedance. Furthermore, the auto-zero technique is applied to the ripple reduction loop for suppressing the second harmonic ripple and maintain operation throughout the loop cycle. A dc servo loop suppresses the electrode dc offset. In <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18~\mu \text{m}$ </tex-math></inline-formula> CMOS process, the proposed AFE IC occupies an active area of 0.99 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , consumes 5.8/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$46.6~\mu \text{A}$ </tex-math></inline-formula> from a 1.8 V supply, and achieves an input impedance above 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{G}{{\Omega }}$ </tex-math></inline-formula> , a CMRR of 102 dB and a PSRR of 72 dB.

0.3V Tunable OTA and Gm-C Filter in 0.13µm CMOS

This paper presents an ultra-low-voltage operational transconductance amplifier (OTA) and Gm-C filter, both working with 0.3V single supply voltage. Using pseudo-differential structure, the common mode rejection is the main challenge in low voltage condition which is overcome by a new common mode feedback circuit. The OTA can be tuned through the gate terminal of body-driven PMOS input transistors. Post-layout simulation shows 23.4 dB differential gain and 47.4 dB CMRR at low frequencies. By changing the tune voltage from 50mV to 0V, the OTA's transconductance can be tuned from 7.9 to 17.4 uA/V. By applying input voltages up to 0.36 Vpp, the THD of output current remains less than -60 dB. The proposed OTA is employed to implement a tunable low-pass Gm-C filter. The cutoff frequency of Gm-C filter can be tuned from 1.13 to 1.9 MHz that makes it applicable in the multi-standard direct conversion receivers as channel selection filter. The power consumption of filter is 111.3 uW and its input referred voltage noise is 168.7 nV/sqrt(Hz), as results of post-layout simulations. The post-layout simulation shows the IIP3 of 8.5 dBm for the cutoff frequency of 1.9 MHz.

Single-Event-Hardened Timing Generator for waveform digitizer based readout electronics

Waveform digitizer, the soul of readout electronics in the radiation detectors performing a multitude of functions has to evade the impact of single-event transients in its timing reference. The propagation of transients from the timing generator to the analog memory causes timing non-linearity due to variation in the inverter delay responsible for the sampling speed leading to catastrophic failure of the waveform sampler. The presented timing generator using mixed-signal delay-locked loop implements the triple combination of the body-feed technique allowing rail-to-rail operation for delay control, the pseudo differential structure regulating duty cycle reduces the jitter and also optimize the linear operating range of the voltage-controlled-delay-line, and the mixed-signal delay-locked loop embedded with dual-edge synchronization enhances the mitigation of single-event upsets. The simulation results at the circuit level using 180 nm and 90 nm CMOS PDKs show a 28% increase in the linear operating range and bettering jitter performance of the mixed-signal delay-locked loop in comparison to the fully differential voltage-controlled-delay-line based delay-locked loop. Furthermore, there is only negligible variance between the irradiated and non-irradiated values for delay interval of each sampling cell and cell-to-cell gain variation in the analog memory of the waveform sampler.

Multi-channel lock-in based differential front-end for broadband Raman spectroscopy

In Broadband Stimulated Raman Spectroscopy, the intrinsic limit given by the laser shot noise is seldom reached due to the electronic noise of the front-end amplifier and the intensity fluctuations of the laser source. In this paper we present a low-noise multi-channel acquisition system, with an integration-oriented design, able to compensate the common-mode fluctuations of the laser output power with the pseudo-differential structure and reach a sensitivity better than 10 ppm thanks to the lock-in technique.

A linear and wide dynamic range transimpedance amplifier with adaptive gain control technique

A linear and wide dynamic range transimpedance amplifier (TIA) for the pulsed time-of-flight imaging LADAR application has been designed and simulated in a 0.18 μm 3.3 V CMOS technology. Specific design techniques, including adaptive gain control technique to widen linear dynamic range, pseudo-differential structure of the front end to decrease the common-mode noise and noise minimization to improve SNR, have been proposed to achieve challenging designs goals with linear dynamic range of 5000:1, high transimpedance gain of 89 dB Ω, bandwidth up to 150 MHz, equivalent input-referred noise current less than 8 $${\text{pA}}/\sqrt {\text{Hz}}$$pA/Hz, in 2 pF photodiode parasitic capacitance. The proposed TIA consumes 165 mW with 3.3 V power supply.

Mellin Operators in the Edge Calculus

A manifold M with smooth edge Y is locally near Y modelled on \(X^\vartriangle \times {\varOmega }\) for a cone \(X^\vartriangle :=(\overline{{\mathbb {R}}}_+\times X)/(\{0\}\times X)\) where X is a smooth manifold and \({\varOmega } \subseteq {\mathbb {R}}^q\) an open set corresponding to a chart on Y. Compared with pseudo-differential algebras, based on other quantizations of edge-degenerate symbols, we extend the approach with Mellin representations on the r half-axis up to \(r=\infty ,\) the conical exit of \(X^{\wedge }={\mathbb {R}}_+\times X\ni (r,x)\) at infinity. The alternative description of the edge calculus is useful for pseudo-differential structures on manifolds with higher singularities.

Recent developments on pseudo-differential operators (II)

The analysis on manifolds with singularities is a rapidly developing field of research, with new achievements and compelling challenges. We present here elements of an iterative approach to building up pseudo-differential structures. Those participate in operator algebras on singular manifolds and reflect the properties of parametrices of elliptic operators, including boundary value problems.

A High Linearity 0.7-2.6 GHz Up-Conversion Mixer

An up-conversion mixer has been designed for 0.7-2.6GHz multi-mode and multi-standard RF subsystem working under 1.8V voltage based on TSMC 0.18μm process in this paper. The circuit is based on the use of pseudo-differential structure of the Gilbert cell, and in order to increase the gain and linearity, is using a complementary trans-conductance current bleeding structure. In addition, a T-type LC networks can reduce the effect of the parasitic capacitance of the LO switching pairs, and make the linearity of the high-frequency greatly improved. Simulation results show that the circuit is working at 0.7-2.6GHz, the gain of the up-conversion is 9.5-9.7dB , the IIP3 of the circuit is 11.4-12.2dBm, and NF is 13.1-13.5dBm.

A novel broadband power amplifier in SiGe HBT technology

A novel broadband power amplifier fabricated in 0.13 μm SiGe HBT technology is realized. The pseudo-differential structure is proposed to avoid the influence of the bonding wire due to the AC virtual ground created at the common emitter node. A compensated matching technique is adopted in interstage matching to expand bandwidth. A multi-stage broadband matching technique is used in an input/output matching network to offer broadband impedance matching, which ensures maximum power transfer. An adaptive bias circuit could improve linearity and efficiency in wide output power level. With 2.5 V power supply, the measured results achieve 96% 3-dB bandwidth (517–1470 MHz), 27.2 dB power gain, 26.9 dBm maximum output power, 19.7 dBm output 1 dB compression point, and 26.7% power added efficiency.

Domino-Logic-Based ADC for Digital Synthesis

A low-power synthesizable analog-to-digital converter (ADC) is presented. By cascading many digital-like domino-logic cells whose propagation delay is influenced by an analog input voltage, a digital value is obtained at the end of the allowed ripple period by determining the number of cells that the ripple passed through. The sample-and-hold is simply a bootstrapped switch into a small sampling capacitor. As each domino-logic cell passes the ripple, charge is kicked back onto the input capacitor, which creates a significant second harmonic. Distortion caused by even harmonics is canceled by implementing a pseudodifferential structure. A test chip is fabricated in 0.18-μm CMOS. The test chip achieves over 5.4-bit effective number of bits up to 50 MS/s with a 1.3-V supply. With a sampling frequency of 50 MS/s and a 24-MHz input, a 34.2-dB signal-to-noise-plus distortion ratio is achieved while consuming 433 μW and occupying only 0.094 mm2.

Design challenges of a fully integrated 65 nm CMOS half cascode SFDS PA

This paper presents the measurement results of a wideband multi-standards fully integrated 65 nm CMOS-power amplifier (PA). This PA is based on a half stacked folded pseudo-differential structure (HSFDS) cascoded. This demonstrator is composed by only one stage. It provides a maximal gain of 10 dB at 2.2 GHz with a bandwidth at ?3 dB (B w -3 dB) of 43%. At 1.95 GHz, the maximal output power (P max ) is 23.3 dBm with a power added efficiency (PAE) of 12%. The output power at 1 dB compression (OCP 1 ) is 21 dBm. At 2.4 GHz, Pmax is 23 dBm with a PAE of 11.3%. At this frequency, the OCP1 is 20 dBm.

Discrete-time charge analysis for a digital RF charge sampling mixer

This paper presents an approach for analyzing the key parts of a general digital radio frequency (RF) charge sampling mixer based on discrete-time charge values. The cascade sampling and filtering stages are analyzed and expressed in theoretical formulae. The effects of a pseudo-differential structure and CMOS switch-on resistances on the transfer function are addressed in detail. The DC-gain is restrained by using the pseudo-differential structure. The transfer gain is reduced because of the charge-sharing time constant when taking CMOS switch-on resistances into account. The unfolded transfer gains of a typical digital RF charge sampling mixer are analyzed in different cases using this approach. A circuit-level model of the typical mixer is then constructed and simulated in Cadence SpectreRF to verify the results. This work informs the design of charge-sampling, infinite impulse response (IIR) filtering, and finite impulse response (FIR) filtering circuits. The discrete-time approach can also be applied to other multi-rate receiver systems based on charge sampling techniques.

A 1-V CMOS Pseudo-Differential Amplifier With Multiple Common-Mode Stabilization and Frequency Compensation Loops

This paper presents an operational amplifier for a 1-V supply voltage. It comprises three gain stages with ac-boosting and buffered Miller feedback compensation circuits. The implementation uses a standard 0.35-mum CMOS process ( V and V). To accommodate maximum voltage headroom between power rails, a pseudo-differential structure is adopted in this amplifier. The large common-mode gain associated with the structure is suppressed by two common-mode stabilization loops. The amplifier driving 100-pF loads achieves a 4.3-MHz gain-bandwidth product. The settling time of a 1- input step signal is 1.1s. The amplifier consumes 249 muW and occupies 0.06-mm silicon area.