pseudo-CMOS Logic Research Articles

Impact of Bias Temperature Instabilities on the Performance of Logic Inverter Circuits Using Different SiC Transistor Technologies

All electronic devices, in this case, SiC MOS transistors, are exposed to aging mechanisms and variability issues, that can affect the performance and stable operation of circuits. To describe the behavior of the devices for circuit simulations, physical models which capture the degradation of the devices are required. Typically compact models based on closed-form mathematical expressions are often used for circuit analysis, however, such models are typically not very accurate. In this work, we make use of physical reliability models and apply them for aging simulations of pseudo-CMOS logic inverter circuits. The model employed is available via our reliability simulator Comphy and is calibrated to evaluate the impact of bias temperature instability (BTI) degradation phenomena on the inverter circuit’s performance made from commercial SiC power MOSFETs. Using Spice simulations, we extract the propagation delay time of inverter circuits, taking into account the threshold voltage drift of the transistors with stress time under DC and AC operating conditions. To achieve the highest level of accuracy for our evaluation we also consider the recovery of the devices during low bias phases of AC signals, which is often neglected in existing approaches. Based on the propagation delay time distribution, the importance of a suitable physical defect model to precisely analyze the circuit operation is discussed in this work too.

Design Methodology for TFT-Based Pseudo-CMOS Logic Array With Multilayer Interconnection Architecture and Optimization Algorithms

Thin-film transistor (TFT) circuits are important for flexible electronics which are promising in the area of wearable devices and Internet of Things. However, most flexible TFT technologies only have unipolar devices and the process variation and defective rate are relatively high, which impose challenges to TFT circuit design. In this paper, we propose a novel logic array design based on pseudo-CMOS logic to address the problems of unipolar TFT circuit design. A multilayer interconnection architecture is presented to improve the routability of circuit and the area efficiency. Cell mapping and wire routing algorithms, which aim to map the logic gates of circuit to logic array and then route the interconnection wires, are devised to improve the performance of circuit in consideration of parameter variations of TFT and meanwhile enhance the routability. The experimental results show that the proposed logic array along with design methodologies can reduce more than 80% area compared with transistor level scheme and help to improve performance significantly.

A digital library for a flexible low-voltage organic thin-film transistor technology

This paper presents the design, fabrication and characterization of digital logic gates, flip-flops and shift registers based on low-voltage organic thin-film transistors (TFTs) on flexible plastic substrates. The organic transistors are based on the p-channel organic semiconductor dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT) and have channel lengths as short as 5 μm and gate-to-contact overlaps of 20 μm. The organic TFT is modeled which allows us to simulate different logic gate architectures prior to the fabrication process. In this study, the zero-VGS, biased-load and pseudo-CMOS logic families are investigated, where their static and dynamic operations are modeled and measured. The inverter and NAND gates use channel length of 5 μm and operate with a supply voltage of 3 V. Static and dynamic master-slave flip-flops based on biased-load and pseudo-CMOS logic are designed, fabricated and characterized. A new design for biased-load dynamic flip-flops is proposed, where transmission gate switches are implemented using only p-channel transistors. 1-stage shift registers based on the new design and fabricated using TFTs with a channel length of 20 μm operate with a maximum frequency of about 3 kHz.

Noise Margin, Delay, and Power Model for Pseudo-CMOS TFT Logic Circuits

Flexibleelectronics based on thin-film transistors (TFTs) are promising in the area of Internet of Things and wearable devices, where the pseudo-CMOS logic is widely used in the unipolar TFT circuits. Though plenty of device models exist, analytical circuit-level models are still absent, preventing the further development of design and analysis of flexible TFT circuits. In this paper, we derive the noise margin (NM), delay, and power models for pseudo-CMOS logic circuits. Furthermore, we simplify thosemodels formanual analysis and design optimization. Allmodels are validated by SPICE simulations, where the device model and its parameters are extracted from the fabricated self-assembled monolayer organic TFTs. The average errors for NM, delay, and power models are 3%, 10%, and 3%, respectively. In addition, we exploit the delay models in a voltage-controlled oscillator design and its linearity of frequency characteristic is optimized with the proposed models, demonstrating their effectiveness.

4H-SiC Pseudo-CMOS Logic Inverters for Harsh Environment Electronics

For logic gate with higher voltage swing, 4H-SiC pseudo-CMOS logic inverter with four nMOS was suggested and demonstrated, and a high voltage swing of 4.4 V was achieved at VDD=5 V. Simple nMOS inverters were also investigated. Both of pseudo-CMOS and nMOS inverters were operated at a high temperature of 200°C. For future SiC large integrated circuits, junction leakage current between n+ regions were also investigated with the comb-shaped test elements.

Flexible thin-film NFC tags

Thin-film transistor technologies have great potential to become the key technology for leaf-node Internet of Things by utilizing the NFC protocol as a communication medium. The main requirements are manufacturability on flexible substrates at a low cost while maintaining good device performance characteristics, necessary to be compatible with the NFC specifications. Such low-cost flexible NFC tags can be attached to any object with any form factor, connecting this object to the Internet using a smartphone or tablet as an intermediate node. Among all commercial thin-film transistor technologies, metal oxide transistors is a viable technology for this application. The metal-oxide transistors in this work are based on InGaZnO as semiconductor. Since these are unipolar by nature (i.e., they exhibit only n-type transistors), different options to make logic circuits are studied from static and dynamic points of view. The different topologies are diode-load logic, dual-gate diode-load logic, and pseudo-CMOS logic. The static parameters lead to a comparison of soft yield between those circuit topologies, while the transient analysis provides insight on the power consumption and circuit speed. This is indicative for selecting the logic style matching the data rate requirements of the NFC standards. Moreover, metal-oxide NFC circuits that combine 12-bit code generators to the analog front-end of RFID tags are integrated on a PCB board to evaluate performance of a matched and optimized system. The measured data rates of these integrated NFC tags are compatible with the ISO 15693 specifications. Finally, a fully integrated, flexible NFC tag is realized, which comprises the tuning capacitor, rectifier, load modulator, and code generator.

Integrated circuits using fully solution-processed organic TFT devices with printed silver electrodes

We have demonstrated fully solution-processed inverter, NAND and NOR circuits using pseudo-CMOS logic and p-type organic TFT devices with printed electrodes that were fabricated using ink-jet printed silver nanoparticle inks at low temperatures. In order to optimize the gate electrode profiles, we thoroughly assessed the surface wettability of the silver nanoparticle inks. The pseudo-CMOS inverter circuit exhibited exceptional switching characteristics with a high signal gain of 34 at a supply voltage of 20V. The NAND and NOR circuits also exhibited excellent logic characteristics, whereby the switching voltage was approximately VDD/2 with a high noise margin and short delay time of 12.5ms.

A Transparent Logic Circuit for RFID Tag in a-IGZO TFT Technology

This paper proposes a transparent logic circuit for radio frequency identification (RFID) tags in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) technology. The RFID logic circuit generates 16-bit code programmed in read-only memory. All circuits are implemented in a pseudo-CMOS logic style using transparent a-IGZO TFTs. The transmittance degradation due to the transparent RFID logic chip is 2.5% to 8% in a 300-nm to 800-nm wavelength. The RFID logic chip generates Manchester-encoded 16-bit data with a 3.2-kHz clock frequency and consumes 170 μW at . It employs 222 transistors and occupies a chip area of 5.85 mm2.

Insole Pedometer With Piezoelectric Energy Harvester and 2 V Organic Circuits

A shoe insole pedometer, which consists of a piezoelectric energy harvester and a 2 V organic pedometer circuit, has been developed as a first step toward the application of flexible large-area energy harvesting. A pseudo-CMOS 14 bit step counter records the number of steps up to 16383 steps using the harvested power. To increase the noise margin of the pseudo-CMOS logic circuits, a negative voltage is generated by an organic charge pump circuit and is applied to the pseudo-CMOS inverters and transmission gates in the flip-flops in the step counter. A pseudo-CMOS Schmitt trigger inverter used to feed clean square pulses to the step counter is presented. This paper describes the details of the insole pedometer and provides measurement results and some discussion.