Protection Circuit Design Research Articles

Design of Driving and protection circuit for Submodule based on cascaded H-bridge STATCOM

Driving and protection circuit is an important part of power electronics, which is related to safe and stable operation issues in the power electronics. The driving and protection circuit is designed for the cascaded H-bridge STATCOM in this paper. The circuit can realize flexible dead-time setting, operation status self-detection, fault priority protection and detailed fault status uploading. It can help to improve the reliability of STATCOM’s operation. Finally, the proposed circuit is tested and analysed by power electronic simulation software PSPICE (Simulation Program with IC Emphasis) and a series of experiments. Further studies showed that the proposed circuit can realize drive and control the H-bridge circuit, meanwhile it also can realize fast processing faults and have advantage of high reliability.

Quench analysis and protection circuit design of a superconducting magnet system for RISP 28GHz ECR ion source

Quench analysis and protection circuit design of a superconducting magnet system for RISP 28GHz ECR ion source

항공기 탑재 컴퓨터용 간접낙뢰 보호장치 개발 및 검증

본 논문에서는 간접낙뢰로 인한 항공기 탑재 컴퓨터의 손상을 보호하기 위한 간접낙뢰 보호장치의 설계 내용 및 시험 과정을 소개한다. 낙뢰로부터 유도된 서지 전압은 항공기 전기 전자장비의 기능 장애나 손상을 가져오는데 이것을 낙뢰의 간접영향이라 한다. 이러한 항공기의 낙뢰 간접영향으로부터 항공전자 장비를 보호하기 위해서는 항공기에 가해진 낙뢰로 인한 영향성을 분석하고 이에 따른 보호 설계를 각각의 장비에 적용한다. 본 논문에서는 보호대상 장비의 간접낙뢰로 인한 손상을 방지하기 위하여 수행한 RTCA DO-160G Section22의 카테고리 분석과 선정을 통한 간접낙뢰 수준 결정, 선정된 레벨에 따른 보호회로 설계 방법을 소개한다. 또한 설계된 보호회로의 유효성 확인을 위해 수행한 낙뢰 간접영향 검증시험 결과를 보인다. This paper introduces the design details and test procedures of the lightning induced transient protection device for protecting the damage caused by indirect lightning strike on the computer mounted on the aircraft. Lightning induced surge voltage is bring a malfunction or damage to the aircraft electrical and electronic equipment, that is referred to indirect effects of lightning. In order to protect the electronic equipment on aircraft from the indirect effects of lightning, that is achieved by analyzing the effect on aircraft from lightning and protect design for each devices. In this paper, we introduce an indirect lightning strike level decisions, the protection circuit design method according to the chosen level through the RTCA DO-160G Section 22 category analysis and selection was performed in order to protect the damage caused by indirect lightning strikes in the protected equipment. In addition, we show the indirect lightning effects verification test performed to validate the designed protection circuits.

A robust electro-thermal IGBT SPICE model: Application to short-circuit protection circuit design

An optimized electro-thermal IGBT SPICE model based on the Kraus model was developed to allow reliable simulation at application level. A particular emphasis to the temperature dependence of physical parameters was given for both the on-state and breakdown conditions. The model was experimentally validated in steady state and transient operation on a Field-Stop trench-gate 30A–600V commercial IGBT device. The effectiveness of the convergence–accuracy aspects was proved for the proposed model. The application to the short-circuit protection circuit design for a hard switched fault in an inverter motor-drive application was also analysed. The ability of the proposed IGBT model was experimentally verified with a simplified-equivalent circuit where a short condition was forced on the load, enabling the desaturation protection by the IGBT driver. The results show an accurate prediction of the device electro-thermal behaviour under short-circuit conditions, with a possible optimal design of the desaturation circuit parameters when the device experiences hard-switched-fault or fault-under-load events.

Design of SCR-Based ESD Protection Circuit for 3.3 V I/O and 20 V Power Clamp

In this paper, MOS-triggered silicon-controlled rectifier (SCR)-based electrostatic discharge (ESD) protection circuits for mobile application in 3.3 V I/O and SCR-based ESD protection circuits with floating N+/P+ diffusion regions for inverter and light-emitting diode driver applications in 20 V power clamps were designed. The breakdown voltage is induced by a grounded-gate NMOS (ggNMOS) in the MOS-triggered SCR-based ESD protection circuit for 3.3 V I/O. This lowers the breakdown voltage of the SCR by providing a trigger current to the P-well of the SCR. However, the operation resistance is increased compared to SCR, because additional diffusion regions increase the overall resistance of the protection circuit. To overcome this problem, the number of ggNMOS fingers was increased. The ESD protection circuit for the power clamp application at 20 V had a breakdown voltage of 23 V; the product of a high holding voltage by the N+/P+ floating diffusion region. The trigger voltage was improved by the partial insertion of a P-body to narrow the gap between the trigger and holding voltages. The ESD protection circuits for low- and high-voltage applications were designed using Bipolar-CMOS-DMOS technology, with width. Electrical characteristics and robustness are analyzed by a transmission line pulse measurement and an ESD pulse generator (ESS-6008).

Protection Circuits for Very High Frequency Ultrasound Systems

The purpose of protection circuits in ultrasound applications is to block noise signals from the transmitter from reaching the transducer and also to prevent unwanted high voltage signals from reaching the receiver. The protection circuit using a resistor and diode pair is widely used due to its simple architecture, however, it may not be suitable for very high frequency (VHF) ultrasound transducer applications (>100 MHz) because of its limited bandwidth. Therefore, a protection circuit using MOSFET devices with unique structure is proposed in this paper. The performance of the designed protection circuit was compared with that of other traditional protection schemes. The performance characteristics measured were the insertion loss (IL), total harmonic distortion (THD) and transient response time (TRT). The new protection scheme offers the lowest IL (-1.0 dB), THD (-69.8 dB) and TRT (78 ns) at 120 MHz. The pulse-echo response using a 120 MHz LiNbO3 transducer with each protection circuit was measured to validate the feasibility of the protection circuits in VHF ultrasound applications. The sensitivity and bandwidth of the transducer using the new protection circuit improved by 252.1 and 50.9 %, respectively with respect to the protection circuit using a resistor and diode pair. These results demonstrated that the new protection circuit design minimizes the IL, THD and TRT for VHF ultrasound transducer applications.

Protection Circuit and Quench Simulation of a 7 T Superconducting Magnet for Animal MRI

A quench protection circuit is designed and the three-dimensional (3-D) thermal-electromagnetic coupled model is built for simulating the quench process of a 7 T actively shielded superconducting magnet for animal MRI. The magnet has a warm bore diameter of 210 mm. It consists of five concentric epoxy-impregnated NbTi/Cu windings and operates in the persistent mode with a total energy of 1.52 MJ. The protection circuit design applies subdivision technology and actively triggered quench heaters, and the 3-D thermal-electromagnetic coupled problem is solved by a commercial finite element method code. To improve the accuracy of analysis, magnetic field and temperature dependence of thermal and electromagnetic characteristics of the magnet materials are taken into account. The hot spot temperature rise of the windings, the temporal variation of the current, and the maximum interlayer voltage are calculated.

Post-Si Programmable ESD Protection Circuit Design: Mechanisms and Analysis

This paper reports new mechanisms, design, and analysis of novel electrostatic discharge (ESD) protection solutions, which enable post-Si field-programmable ESD protection circuit design for the first time. Two new ESD protection concepts, nano-crystal quantum-dot (NC-QD) and silicon–oxide–nitride–oxide–silicon (SONOS)-based ESD protection, are presented. Experiments validated the two new programmable ESD protection mechanisms. Prototype designs demonstrated a wide adjustable ESD triggering voltage $({V}_{{t}1})$ range of $\Delta{V}_{{t}1}\sim \hbox{ 2 V}$ , very fast response $({t}_{1})$ to ESD transients of rising time ${t}_{r}\sim \hbox{ 100 pS}$ and pulse duration ${t}_{d}\sim \hbox{ 1 nS}$ , ESD protection capability $({I}_{{t}2})$ of at least 25 $\hbox{mA}/\mu\hbox{m}$ for human body model (HBM) and 400 $\hbox{mA}/\mu\hbox{m}$ for charged device model (CDM) equivalent stressing, and very low leakage current $({I}_{\rm leak})$ as low as 1.2 pA. Field-programmable ESD protection circuit design examples are discussed.

The Transient Process Analyse of the Circuit with a Resistance-Capacitance Branch

In this paper the auther made deep research on the principle and the transient process of resistance-capacitance over voltage protection circuit in different working condition during the electric locomotive running, and based on the analysis of the Circuit Transient Process, obtained the theoretic expressions of the voltage and the current of the resistance and the expression of the energy absorbed by the resistance during the working process. The research offers theoretical basis for design and improvement of the resistance-capacitance protection circuit.

The Application of SG3525 Pulse Width Modulator in Intermediate Frequency Induction Heating Power Supply

In This paper, we introduce a kind of intermediate frequency induction heating power supply integral design based on the pulse width modulator SG3525, analyse SG3525, KA962F driving chip, the main circuit structure and function and realize frequency and occupies emptiescompared independent can be adjusted. The main circuit adopts the series resonant type IGBT half bridge inverter circuit. It outputs pulse with difference of two phases of 180 degrees to the IGBT driver board through the SG3525, IGBT driver board receives the pulse and drive the IGBT main circuit. Circuit adds the limit frequency protection circuit design, so that the heating power supply works in the inductive state. To improve the on-site operation safety.Finally the unit circuit experiment is conducted on the basis of the field experiment, it is proved that the whole design scheme is feasibility by experiments.

Overheat protection circuit for high frequency processors

Overheat protection circuit for high frequency processors The paper describes design and structure of the overheat protection circuit based on the PTAT sensors. The digital core of the system is driven by a 3-bit information generated by the structure. As a result, behaviour of the core differs for each temperature. The circuit was designed in LF CMOS 0.15 μm technology using full-custom technique. The presented paper focuses especially on the structure of the overheat protection circuit and simulations results of the functional blocks of the system. Layout and some parameters of the circuit are also considered.

Final Design of the Quench Protection Circuits for the JT-60SA Superconducting Magnets

This paper describes the detailed design of the quench protection circuits (QPCs) for the superconducting toroidal field (TF) and poloidal field (PF) magnets of the satellite tokamak JT-60SA, which will be installed in Naka, Japan. The nominal currents to be interrupted and the maximum reapplied voltages are 25.7 kA and 2.8 kV for the TF QPCs and 20 kA and 5 kV for the PF QPCs. The innovative solution proposed in the QPC design is based on a hybrid circuit breaker (CB) composed of a mechanical bypass switch for conducting the continuous current, in parallel to a static CB for current interruption. The main choices of the final design are presented and discussed, either to confirm or to update and complete the study performed at the conceptual design level.

Design of Self-Adaptive ZVS Protection Circuit for Electronic Ballast

The overlap of the voltage and current of power MOSFET will leads large power loss when power MOSFET in a ballast turns on. To solve this problem, a self-adaptive ZVS protection circuit is proposed, which consists of a dead time control circuit and a ZVS control circuit. Compared with traditional circuit with fixed dead time, it can regulate the dead-time automatically to realize ZVS with a negative feedback loop and result reduction advantages come from, such as the induction of power loss and EMI, meanwhile the efficiency is improved. Hspice simulation shows that the ZVS protection circuit in the ballast with an input voltage of 14V and an operation frequency of 50 kHz can realize the self-adaptive dead time.

Design of a hiccup mode over-current protection circuit for DC–DC switching converters

In the paper an improvement hiccup mode over-current protection circuit is proposed and successfully applied in a typical current-mode DC–DC switching converter. It greatly reduces the circuit power consumption in prolonged overload conditions and can provide smooth self-recovery once the overload condition is removed. By reducing the switching frequency and over-current threshold value, it further improves the effect of over-current protection. The power consumption and implementation area are minimized by digital control. By simulation and verification with HSPICE, the output average current is only 16.8% of the conventional over-current mode in continuous over-current conditions. The presented circuits can automatically recover with the maximum load (5A) when the overload is removed.

Analysis and Design of IGBT Driving and Protection Circuit for Photovoltaic Grid-Connected Inverter

For the characteristics of high frequency of switching devices in the photovoltaic inverter and complexity of circuit topology, the insulated gate bipolar transistor driving protection circuit is designed which is suitable for photovoltaic inverter. The circuit which is based on thick film structure of M57962L has isolated power supply and threshold voltage regulator circuits. The control and regulation can be achieved precisely for the threshold voltage of over current protection. The internal structure of M57962L has been analyzed here. The process of slow turn off action is observed practically. For the circuit periphery parameters of M57962L, the general calculation methods are given according to various models and the level of protection for IGBT. The practical application shows that the method is correct and effective.

Design and Realization of an Intelligent Protection Circuit for Li-Ion Batteries

Li-ion batteries have been widely used. However, the safety concern is always serious due to its high energy density. In order to improve the safety of the batteries, it is necessary to use the protection integration circuit. In this article, the concept for realizing the safety protection of Li-ion batteries during charging and discharging is described briefly. A circuit design using Seiko BMS chip S-8209 is purposed. Based on this, a simulation was performed and verified using Pspice program, which provides a theoretical basis for the circuit design.

Characteristics analysis and optimization design of a new ESD power clamp circuit

As CMOS technology scales down, the design of ESD protection circuits becomes more challenging. There are some disadvantages for the actual power clamp circuit. In this paper, an optimization ESD power clamp circuit is proposed. The new clamp circuit adopts the edge triggering True Single Phase Clocked Logic (TSPCL) D flip-flop to turn on and time delay, it has the advantage of dynamic transmission structure. By adding a leakage transistor of small size, the clamp circuit can turn off effectively. By changing the W/ L ratio, the clamp can safely protect the gate of ESD power clamp devices from thermoelectric breakdown. The results show that the circuit can reduce the false triggering and power supply noise more effectively, it can be widely used in high-speed integrated circuits. The proposed structure has the advantages of low power and low cost, and can be used to the system-level ESD protection.

Conceptual design of the quench protection circuits for the JT-60SA superconducting magnets

In JT-60SA, the new satellite tokamak to be built in Naka, Japan, the magnetic field for plasma generation and confinement is produced by a number of superconducting coils whose rated current ranges from 20 kA to 25.7 kA, with a nominal voltage up to 5 kV. This paper deals with the conceptual design of the Quench Protection Circuits (QPC) of JT-60SA, which must provide a fast removal of the energy stored in the superconducting coils in case of quench. The core of the QPC units is based on a dc current breaker, which diverts the coil current into a discharge resistor. Different concepts of dc circuit breaker for QPC were considered, including vacuum and static circuit breakers; then, a hybrid solution, composed of a mechanical bypass switch paralleled to a static switch based on Integrated Gate Commutated Thyristor (IGCT) technology, has been worked out. A pyrobreaker is added in series to the hybrid switch as a backup protection. The resulting design allows benefiting from the fast breaking and very low maintenance requirement of the static switches, besides maintaining the advantage of the much lower power losses of the mechanical bypass in normal operation. After a brief presentation of the preliminary studies, the selected design solution for JT-60SA is presented in detail.

ESD protection strategies in advanced CMOS SOI ICs

This paper represents a part of the ESREF 2007 tutorial on the design of IC protection circuits built with advanced deep sub-micron CMOS silicon-on-insulator (SOI) technologies. The tutorial covers fundamental aspects of active rail clamp Electrostatic Discharge (ESD) protection approach to meet the human body model (HBM), machine model (MM), and charged device model (CDM) requirements in SOI ICs. The paper focuses on 65 nm SOI ESD protection network and design methodology including both device and circuit level characterization data. It compares pulsed measurement results of SOI MOSFETs and diodes to bulk devices. It also introduces a response surface method (RSM) to optimize device sizes in the ESD networks.

Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits

CDM ESD event has become the main ESD reliability concern for integrated-circuits products using nanoscale CMOS technology. A novel CDM ESD protection design, using self-biased current trigger (SBCT) and source pumping, has been proposed and successfully verified in 0.13-μm CMOS technology to achieve 1-kV CDM ESD robustness.