Proposed XOR Gate Research Articles

QCA-based fault-tolerant XOR Gate for reliable computing with high thermal stability

The XOR gate is an essential element in the design of digital circuits due to its versatility and usefulness. The design of XOR gate in this paper is based on Quantum-dot Cellular Automata (QCA) 2D planner technology with no line-to-line intersections. The output amplitude is improved by redundant cell-based design, which also helped reliability and fault tolerance outperform. The proposed XOR gate achieves fault tolerance to single-cell addition and missing-cell defects from 68.48% to 95.33%. In addition, the proposed XOR gate is also fault-tolerant against multiple-cell missing defects, as verified from the simulations. Furthermore, high thermal stability makes the circuit reliable for QCA-based digital design applications. The digital design applications such as 4-bit B2G code converter and a 4-bit parity checker are designed from this XOR gate, utilizing 438 and 414 cells, respectively. This demonstrates its effectiveness in designing fault resilient and reliable circuit designs for various applications.

Notice of Violation of IEEE Publication Principles: Design of Cost Efficient Modular Digital QCA Circuits using Optimized XOR Gate

Notice of Violation of IEEE Publication Principles “Design of Cost Efficient Modular Digital QCA Circuits using Optimized XOR Gate” by Suhaib Ahmed and Syed Farah Naz in IEEE Transactions on Circuits and Systems II: Express Briefs After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE’s Publication Principles. This paper contains significant portions of original text from the paper cited below. The original text was copied without attribution (including appropriate references to the original author(s) and/or paper title) and without permission. “Design and Analysis of a Novel Low-Power Exclusive-OR Gate Based on Quantum-Dot Cellular Automata” By Haotian Chen, Hongjun Lv, Zhang Zhang, Xin Cheng and Guangjun Xie in Journal of Circuits, Systems, and Computers, Vol. 28, No. 8, 2017 The advantages such as high operating frequency (in the range of few THz), low power dissipation, small size and high density in the nano regime has led to the application of Quantum dot Cellular Automata (QCA) in designing various digital circuits. In this brief, an ultra-efficient two input XOR gate design in QCA is proposed. It is a single layer design consisting of only 9 cells with no crossover and operating on cell to cell interaction. The functionality of the proposed gate has been verified at both physical and simulation level. In addition to this, fault tolerance to single cell missing defect, single cell addition defect and single cell displacement defect of the proposed XOR gate has also been presented. Based on the performance evaluation, it is seen that the proposed XOR gate has least cell count, least area and least latency which in turn leads to least circuit cost. Also, the proposed design dissipates least energy. The applicability of proposed XOR gate has also been investigated by designing various cost efficient digital circuits such as full adder, parity checker, etc.

Multi-Layered QCA Content-Addressable Memory Cell Using Low-Power Electronic Interaction for AI-Based Data Learning and Retrieval in Quantum Computing Environment.

In this study, we propose a quantum structure of an associative memory cell for effective data learning based on artificial intelligence. For effective learning of related data, content-based retrieval and storage rather than memory address is essential. A content-addressable memory (CAM), which is an efficient memory cell structure for this purpose, in a quantum computing environment, is designed based on quantum-dot cellular automata (QCA). A CAM cell is composed of a memory unit that stores information, a match unit that performs a search, and a structure, using an XOR gate or an XNOR gate in the match unit, that shows good performance. In this study, we designed an XNOR gate with a multilayer structure based on electron interactions and proposed a QCA-based CAM cell using it. The area and time efficiency are verified through a simulation using QCADesigner, and the quantum cost of the proposed XOR gate and CAM cell were reduced by at least 70% and 15%, respectively, when compared to the latest research. In addition, we physically proved the potential energy owing to the interaction between the electrons inside the QCA cell. We also proposed an additional CAM circuit targeting the reduction in energy dissipation that overcomes the best available designs. The simulation and calculation of power dissipation are performed by QCADesigner-E and it is confirmed that more than 27% is reduced.

Design and Implementation of New Coplanar FA Circuits without NOT Gate and Based on Quantum-Dot Cellular Automata Technology

The miniaturization of electronic devices and the inefficiency of CMOS technology due to the development of integrated circuits and its lack of responsiveness at the nanoscale have led to the acquisition of nanoscale technologies. Among these technologies, quantum-dot cellular automata (QCA) is considered one of the possible replacements for CMOS technology because of its extraordinary advantages, such as higher speed, smaller area, and ultra-low power consumption. In arithmetic and comparative circuits, XOR logic is widely used. The construction of arithmetic logic circuits using AND, OR, and NOT logic gates has a higher design complexity. However, XOR gate design has a lower design complexity. Hence, the efficient and optimized XOR logic gate is very important. In this article, we proposed a new XOR gate based on cell-level methodology, with the expected output achieved by the influence of the cells on each other; this design method caused less delay. However, this design was implemented without the use of inverter gates and crossovers, as well as rotating cells. Using the proposed XOR gate, two new full adder (FA) circuits were designed. The simulation results indicate the advantage of the proposed designs compared with previous structures.

Design of reversible Feynman and double Feynman gates in quantum-dot cellular automata nanotechnology

PurposeThis paper aims to propose the reversible Feynman and double Feynman gates using quantum-dot cellular automata (QCA) nanotechnology with minimum QCA cells and latency which minimizes the circuit area with the more energy efficiency.Design/methodology/approachThe core aim of the QCA nanotechnology is to build the high-speed, energy efficient and as much smaller devices as possible. This brings a challenge for the designers to construct the designs that fulfill the requirements as demanded. This paper proposed a new exclusive-OR (XOR) gate which is then used to implement the logical operations of the reversible Feynman and double Feynman gates using QCA nanotechnology.FindingsQCA designer-E has been used for the QCA designs and the simulation results. The proposed QCA designs have less latency, occupy less area and have lesser cell count as compared to the existing ones.Originality/valueThe latencies of the proposed gates are 0.25 which are improved by 50% as compared to the best available design as reported in the literature. The cell count in the proposed XOR gate is 11, while it is 14 in Feynman gate and 27 in double Feynman gate. The cell count for the proposed designs is minimum as compared to the best available designs.

The Design of Low Power High Speed Two Level Three input XOR gate

The Large Fan-In and high performance gates are essential to make portable electronic devices. In this paper an efficient realization of three input two level XOR(Exclusive-OR) is presented. The design of low power and high speed proposed XOR gate involves the combination of pass and transmission gates. The main objective to achieve this is based on the selection of input signals to propagate and maintain the good logic swing. Two methods were used to design proposed XOR, one (i.e. Pass_gate) is purely based on pass transistors with 8 MOSFET’s and second method(Modified_Pass_gate) uses transmission gates with 12 transistors. The Modified_Pass_gate offers 86.14% and 6.66% of power dissipation reduction compared to static and Pass_gate XOR respectively and 77.18% and 50.94% less propagation delay compared to static and Pass_gate XOR respectively, at the supply voltage of 0.7v with input signal frequency of 3GHz. The simulation is performed based on 32nm technology node(PTM-models) using Hspice Synopsis simulation tool.

Full Adder Circuit Design with Novel Lower Complexity XOR Gate in QCA Technology

Quantum-dot Cellular Automata (QCA) is a new technology for designing digital circuits in Nanoscale. This technology utilizes quantum dots rather than diodes and transistors. QCA supplies a new computation platform, where binary data can be represented by polarized cells, which can define by the electron’s configurations inside the cell. This paper explains QCA based combinational circuit design; such as half-adder and full-adder, by only one uniform layer of cells. The proposed design is accomplished using a novel XOR gate. The proposed XOR gate has a 50% speed improvement and 35% reduction in the number of cells needed over the best reported XOR. The results of QCADesigner software show that the proposed designs have less complexity and less power consumption than previous designs.

Design and Analysis of a Novel Low-Power Exclusive-OR Gate Based on Quantum-Dot Cellular Automata

Recently reported quantum-dot cellular automata (QCA) exclusive-OR gate designs are usually made with the AND–OR–INVERTER method in which it is difficult to optimize the XOR gate. This paper presents a novel low-power exclusive-OR (XOR) gate which is mainly based on cell-level format. Compared with the previous XOR gates, the proposed XOR gate performs in a different manner. This XOR gate design is accomplished by the intercellular effects method. For better performance comparison with previous relevant works, 4-, 8-, 16- and 32-bit parity generators are implemented in this paper. The simulation results show that there is a reduction of 32.5% cell count and 21.5% area in comparison with the existing advanced 32-bit parity generator. Especially in the aspect of clock cycle, the proposed design reduces the delay by 50% compared to the previous design. For simulation analysis, QCADesigner tool is used to verify the correctness of the proposed design. QCApro tool is used to evaluate the power dissipation of this design.

Stateful Memristor-Based Search Architecture

Computer vision and recognition is emerging as one of the important pillars in artificial intelligence systems. It is a vital way to interpret the collected data and find matching patterns that will help in real-time decision making. CMOS-based search engines suffer from density and power limitations. Memristor is a feasible candidate that is capable of performing search within a stored structure (in-memory computing). This paper proposes the first memristor-based stateful search engine architecture based on a novel stateful heterogeneous memristive XOR gate. The design is suitable for 2-D media applications, such as image matching and pattern inspection. It performs bitwise comparison using the proposed XOR gate. The output states of all XOR gates are transferred into a single analog memristor value that is read via a digital comparator. The design assumes a single memristor device for each of the incoming data, template, and result bits. Each 2-D array of input, template, and output is reordered into a single 1-D array with $3\times (N\times M$ ) structure, where $N$ represents the number of entry data and $M$ is the number of bits per entry. This allows for a significantly higher storage density than conventional CMOS-based or other memristor-based search engines. Simulations of the proposed architecture demonstrate functionalities in search and compare modes using an LTSpice circuit simulator. The proposed architecture achieves a 3-ns search cycle time at 0.34 nJ/database at 1.5 V/1 GHz using $2N+1$ memristors.

A revolution in nanostructure designs by proposing a novel QCA full-adder based on optimized 3-input XOR

Quantum-dot cellular automata is one of the best alternative technologies of CMOS at nano-scale. It is an emerging technology promising to design circuits with low power consumption, high density as well as high speed. In this paper, a novel 3-input XOR gate based on the cellular interaction is first proposed which consists of 10 cells and requires two clocks. To demonstrate the efficiency of the proposed XOR gate, an optimized single-layer full-adder is designed here which contains only 20 cells and requires three clock phases. In order to verify the function of the proposed full-adder, some physical proofs and computer simulations are provided. The simulations are carried out by QCADesigner2.0.3. The proposed full-adder shows 24% and 9.09% improvement in cell count in comparison to the best previous single-layer and multi-layer full-adder designs, respectively. In addition, the power consumption of the proposed full-adder is calculated by QCAPro tool. The results of power dissipation analysis show that the proposed full-adder has the lowest energy consumption compared to the previous designs.

A novel low power Exclusive-OR via cell level-based design function in quantum cellular automata

This paper presents a new low power two-input Exclusive-OR gate based on quantum cellular automata. The proposed XOR gate performs in a different manner from conventional previous XOR gates, which are mainly based on cell leveled format. Common XORs are designed utilizing AND-OR-INVERTER method. For the proposed new design, the XOR gate is implemented based on QCA cell interaction directly. To explore the efficiency of the proposed design in large area and complex QCA structures, even parity generator circuits with 4, 8, 16 and 32 bits lengths are implemented. The simulation results demonstrate better performance of the proposed design in comparison with previous design in terms of area, latency and energy dissipation. We demonstrate correctness functionality of the proposed architectures using QCADesigner as a simulator tool. The energy dissipation of proposed design has been evaluated by QCAPro tool.

A novel 3-input XOR function implementation in quantum dot-cellular automata with energy dissipation analysis

Quantum dot-cellular automata (QCA) are one of novel emerging nanotechnology, which seem to be excellent alternatives to the conventional complementary metal-oxide semiconductor (CMOS) technology. QCA technology has a wide range of optimize facet such as ultra-low power consumption, faster switching speed and extremely density structure. In this paper, a novel exclusive-OR (XOR) gate is presented. This proposed XOR gate requires only 12 cells and dissipates 12.11meV energies at 1.0Ek tunneling energy level. To inspect the efficacy of proposed XOR gate, new QCA design of half and full subtractor is introduced here. In comparison with previous QCA designs, the proposed layouts are implemented with the minimum area, minimum number of cells and delay without any wire-crossing techniques. The proposed, half and full subtractors require 19 and 32 cells and occupy 0.0186μm2 and 0.0287μm2 area respectively. To validate the accuracy of the proposed design, QCADesigner, a familiar QCA simulation tool is employed.

Towards ultra-efficient QCA reversible circuits

Nanotechnologies, remarkably Quantum-dot Cellular Automata (QCA), offer an attractive perspective for future computing technologies. In this paper, QCA is investigated as an implementation method for reversible logic. A novel XOR gate and also a new approach to implement 2:1 multiplexer are presented. Moreover, an efficient and potent universal reversible gate based on the proposed XOR gate is designed. The proposed reversible gate has a superb performance in implementing the QCA standard benchmark combinational functions in terms of area, complexity, power consumption, and cost function in comparison to the other reversible gates. The gate achieves the lowest overall cost among the most cost-efficient designs presented so far, with a reduction of 24%. In order to employ the merits of reversibility, the proposed reversible gate is leveraged to design the four common latches (D latch, T latch, JK latch, and SR latch). Specialized structures of the proposed circuits could be used as building blocks in designing sequential and combinational circuits in QCA architectures.

New Proposal for MCML Based Three-Input Logic Implementation

This paper presents a new proposal for three-input logic function implementation in MOS current mode logic (MCML) style. The conventional realization of such logic employs three levels of stacked source-coupled transistor pairs. It puts restriction on minimum power supply requirement and results in increased static power. The new proposal presents a circuit element named as quad-tail cell which reduces number of stacked source-coupled transistor levels by two. A three-input exclusive-OR (XOR) gate, a vital element in digital system design, is chosen to elaborate the approach. Its behavior is analyzed and SPICE simulations using TSMC 180 nm CMOS technology parameters are included to support the theoretical concept. The performance of the proposed circuit is compared with its counterparts based on CMOS complementary pass transistor logic, conventional MCML, and cascading of existing two input tripple-tail XOR cells and applying triple-tail concept in conventional MCML topology. It is found that the proposed XOR gate performs best in terms of most of the performance parameters. The sensitivity of the proposed XOR gate towards process variation shows a variation of 1.54 between the best and worst case. As an extension, a realization of 4 : 1 multiplexer has also been included.

MOS current mode logic exclusive-OR gate using multi-threshold triple-tail cells

This paper presents a modified low-voltage MOS current mode logic (MCML) exclusive-OR (XOR) gate. The proposed topology introduces multiple threshold voltage transistors in the triple-tail cell of a MCML XOR gate. This scheme allows reduction in the implementation area of a triple-tail cell and the logic gate employing it. The impact of employing multiple threshold voltage transistors on the operation of the XOR gate is investigated; and mathematical formulations for the static and delay parameters are derived. A design procedure based on the static model is put forward. The accuracy of the models is verified by designing and simulating the proposed XOR gate for wide operating conditions. The model parameters of TSMC 0.18µm CMOS technology are used. An assessment in terms of implementation area and the process variations is conducted for the proposed and the available XOR gates. Finally, the performance of all the XOR topologies is compared for different design cases and the favorable cases are identified.

Shannon’s expansion theorem-based multiplexer synthesis using QCA

Quantum dot-cellular automata (QCA) achieved their fame in designing low-power nanodevices for logic computation. Shannon’s expansion theorem helps to achieve a design for digital logic circuits that has three or more levels of logic with minimum implementation cost – that is, a smaller number of logic gates. Moreover, Shannon’s expansion theorem reduces the number of fan-in of the given circuits and the required inputs to a gate input. Thus, the QCA-based realization of a logic circuit will have fewer majority gates due to the use of Shannon’s theorem, which will reduce the circuit complexity, the latency and the energy dissipation. In this paper, the QCA-based realization of a three-input exclusive OR (XOR) gate using a 2:1 multiplexer is performed. Shannon’s expansion theorem is used to achieve the minimum implementation cost for the proposed XOR gate. With respect to the individual input variable to this XOR gate, the implementation cost in terms of the required logic gates is estimated. The estimation reflects that the cost is the same no matter which input variable is used to expand. The design of such a circuit promises to yield considerable results within the QCA research community.

Flexible and re-configurable optical three-input XOR logic gate of phase-modulated signals with multicast functionality for potential application in optical physical-layer network coding.

Optical logic gate, especially exclusive-or (XOR) gate, plays important role in accomplishing photonic computing and various network functionalities in future optical networks. On the other hand, optical multicast is another indispensable functionality to efficiently deliver information in optical networks. In this paper, for the first time, we propose and experimentally demonstrate a flexible optical three-input XOR gate scheme for multiple input phase-modulated signals with a 1-to-2 multicast functionality for each XOR operation using four-wave mixing (FWM) effect in single piece of highly-nonlinear fiber (HNLF). Through FWM in HNLF, all of the possible XOR operations among input signals could be simultaneously realized by sharing a single piece of HNLF. By selecting the obtained XOR components using a followed wavelength selective component, the number of XOR gates and the participant light in XOR operations could be flexibly configured. The re-configurability of the proposed XOR gate and the function integration of the optical logic gate and multicast in single device offer the flexibility in network design and improve the network efficiency. We experimentally demonstrate flexible 3-input XOR gate for four 10-Gbaud binary phase-shift keying signals with a multicast scale of 2. Error-free operations for the obtained XOR results are achieved. Potential application of the integrated XOR and multicast function in network coding is also discussed.

A new F-shaped XOR gate and its implementations as novel adder circuits based Quantum-dot cellular Automata (QCA)

Quantum-dot cellular automata (QCA) is a novel nanotechnology that promises smaller size, lower power consumption, with faster speed and is considered as a solution to the scaling problems in complementary metal oxide semiconductor technology. We propose a novel QCA F-shaped XOR gate. The proposed gate is simple in structure and powerful in terms of implementing digital circuits. We implement novel adder circuits like half adders and half subtractors by introducing the proposed XOR gate. The proposed adder circuits are simple in design and occupy a fraction of area, as compared to previous designs. These circuits are suitable for optimizing the complex structures. Simulation results demonstrate that the new structures have achieved significant improvements in terms of circuit complexity. The functionality of proposed structures have been checked by QCADesigner tool.

DDR4/GDDR5에서 고속동작을 위한 matrix형 CRC 및 XOR/XNOR

DDR4와 같은 고속동작을 위한 메모리 제품에서, 데이타의 신뢰도 증가를 위해 CRC 기능이 추가되었다. 기존의 CRC 방식은 많은 부가회로 면적과 지연시간이 요구되기 때문에 고속동작의 메모리 제품에서 CRC 계산을 위한 내부 타이밍 마진의 부족현상이 증가한다. 따라서 본 논문에서는 이러한 문제를 해결할 수 있도록 matrix형 CRC 방법을 제시하고 CRC 계산을 빠르게 할 수 있는 XOR/XNOR 게이트를 제시하였다. matrix형 CRC는 모든 홀수 비트오류를 검출 가능하며, 4의 배수비트 오류를 제외한 짝수비트오류도 검출가능하다. 또한 단일오류(single error)에 대해서는 오류 정정이 가능하여 메모리 제품과 시스템간의 CRC 오류로 인한 데이터 재 전송의 부하를 감소시킬 수 있다. 또한 기존 방식대비 부가회로면적을 57% 개선할 수 있다. 제안한 XOR/XNOR는 6개의 TR.(트랜지스터)로 구성하였으며, 기존의 CRC 대비 35%의 면적 오버헤드를 감소시킬 수 있으며, 50%의 게이트 지연을 감소시킬 수 있다.

Eliminating the additional input beam in all-optical XOR gate using Terahertz Optical Asymmetric Demultiplexer (TOAD) based interferometer: A theoretical analysis

All-Optical XOR Logic is a key technology for performing a set of operations in optical time division multiplexing (OTDM) multi-access network. In this paper an All-Optical Boolean XOR logic gate with Terahertz Optical Asymmetric Demultiplexer (TOAD) based interferometric switch is designed and described. In this proposed XOR gate, no additional input light source is used. Numerical simulation is also presented, which verifies the theoretical results. Contrast ratio, extinction ratio, amplitude modulation, bit error rate and signal to noise ratio values have also been analyzed.