Proposed Ultra-wideband Low Noise Amplifier Research Articles

A high linearity low power low-noise amplifier designed for ultra-wide-band receivers

This paper presents a new ultra-wide band (UWB) CMOS low noise amplifier (LNA) with very high linearity and low power consumption for UWB wireless communication applications, where linearity is a big challenge, due to presence of interference and blocker signals, as well as the in-band harmonics of the desired signal components in the lower part of UWB band. The proposed LNA uses a new combination of saturated NMOS and PMOS transistors to improve both of second order and third order nonlinearities, meanwhile improving the noise performance and DC power consumption. In our design two techniques are integrated in a novel approach: Improved Complementary Derivative Superposition (ICDS) technique and Forward Body Bias (FBB) to reduce the threshold voltage of MOSFET, and hence, lowering the DC power. By utilizing a high-pass filter and common source stage in cascode form, wideband impedance matching and optimal noise figure (NF) have been obtained in the proposed UWB–LNA. The Post-layout simulation of the linearized LNA in a 180 nm RF CMOS process shows NF between 2.5 and 4 dB, gain of 10.8 ± 0.5 dB, and S11 less than −10 dB in the entire 3.1–10.6 GHz band. Total DC power consumption is only 6 mW with 1.2 V supply voltage. The average and the maximum of IIP3 in the UWB band are + 3.84 dBm and + 7.27 dBm, respectively, a superior linearity performance compared to the reported UWB ones. The chip area is 926 mm × 1075 mm, including the supply and ESD ring and the pads.

Design of a high linear and ultra-wideband LNA using post distortion star feedback method

In this paper, a CMOS low noise amplifier (LNA) with very high linearization for ultra-wideband (UWB) applications is presented. In the proposed LNA, both second- and third-intercept points (IIP2 and IIP3) are improved by the new suggested post distortion star feedback (PDSF) technique in a wide frequency range. The star feedback circuit consists of three resistors that eliminate the nonlinear effect of the cascade transistor, and the PD circuit has an auxiliary transistor that eliminates the third-order non-linear coefficient of the main transistor. The post-layout simulation results of the proposed UWB LNA, which is designed using TSMC RF CMOS 65 ​nm, show the maximum power gain of 11 ​dB, minimum NF of 3.2 ​dB, and average IIP3 of 24 dBm in the frequency range of 3.1–10.6 ​GHz. In the designed circuit, the maximum IIP2 of 23.4 dBm is achieved. The chip area of the circuit is 0.874 ​mm2, while the LNA consumes 15 ​mW from a 1.2 ​V supply voltage.

A band-selective CMOS low-noise amplifier with current reuse gm boosting technique for 3-5 GHz UWB receivers

The authors have proposed a 3-5 GHz ultra-wideband (UWB) low power and low noise amplifier (LNA) with the TSMC 0.18 μm RF CMOS process, which uses a novel dual input matching network for wideband matching. We have used a current-reuse gm-boosted common-gate topology and shunt-shunt feedback common-source output buffer to improve gain and noise figure with low power dissipation. The proposed dual input matching gm-boosted common-gate LNA has been efficient bandwidth to cover UWB band. It has required less inductors or amplification stages to increase bandwidth as compared with the conventional UWB common-gate LNAs. The broadband input stage has been able to be switched to three frequency bands with capacitive switches. The capacitive switch has replaced a large inductor to resonate at lower frequency band. The band-selective LNA has shown linearity improvement by attenuating the undesired interference of a wideband gain circuit and using less inductors. Simulated performance has shown the gains of 15.9, 17.6, and 16.9 dB, and the noise figures of 3.38, 3.28, and 3.27 dB at the 3.432, 3.960, and 4.488 GHz frequency bands, respectively. The proposed UWB LNA has consumed 5 mW from a 1.8-V power supply.

A High Gain, Noise Cancelling 3.1-10.6 GHz CMOS LNA for UWB Application

With the rapid development of ultra-wideband communications, the design requirements of CMOS radio frequency integrated circuits have become increasingly high. Ultra-wideband (UWB) low noise amplifiers are a key component of the receiver front end. The paper designs a high power gain (S₂₁) and low noise figure (NF) common gate (CG) CMOS UWB low noise amplifier (LNA) with an operating frequency range between 3.1 GHz and 10.6 GHz. The circuit is designed by TSMC 0.13 μm RF CMOS technology. In order to achieve high gain and flat gain as well as low noise figure, the circuit uses many technologies. To improve the input impedance matching at low frequencies, the circuit uses the proposed T-match input network. To decrease the total dissipation, the circuit employs current reused technique. The circuit uses he noise cancelling technique to decreases the NF. The simulation results show a flat S₂₁>20.81 dB, the reverse isolation (S₁₂) less than -48.929 dB, NF less than 2.617 dB, the minimum noise figure (NF_min)=1.721 dB, the input return loss (S11) and output return loss (S₂₂) are both less than -14.933 dB over the frequency range of 3.1 GHz to 10.6 GHz. The proposed UWB LNA consumes 1.548 mW without buffer from a 1.2 V power supply.

A 3.1–10.6 GHz UWB LNA Based on Self Cascode Technique for Improved Bandwidth and High Gain

In this work, we present a self cascode based ultra-wide band (UWB) low noise amplifier (LNA) with improved bandwidth and gain for 3.1–10.6 GHz wireless applications. The self cascode (SC) or split-length compensation technique is employed to improve the bandwidth and gain of the proposed LNA. The improvement in the bandwidth of SC based structure is around 1.22 GHz as compared to simple one. The significant enhancement in the characteristics of the introduced circuit is found without extra passive components. The SC based CS–CG structure in the proposed LNA uses the same DC current for operating first stage transistors. In the designed UWB LNA, a common source (CS) stage is used in the second stage to enhance the overall gain in the high frequency regime. With a standard 90 nm CMOS technology, the presented UWB LNA results in a gain $$\hbox {S}_{21}$$ of $$20.10 \pm 1.65\,\hbox {dB}$$ across the 3.1–10.6 GHz frequency range, and dissipating 11.52 mW power from a 1 V supply voltage. However, input reflection, $$\hbox {S}_{11}$$ , lies below $$-\,10$$ dB from 4.9–9.1 GHz frequency. Moreover, the output reflection ( $$\hbox {S}_{22}$$ ) and reverse isolation ( $$\hbox {S}_{12}$$ ), is below $$-\,10$$ and $$-\,48$$ dB, respectively for the ultra-wide band region. Apart from this, the minimum noise figure ( $$\hbox {NF}_{min}$$ ) value of the proposed UWB LNA exists in the range of 2.1–3 dB for 3.1–10.6 GHz frequency range with a a small variation of $$\pm \,0.45\,\hbox {dB}$$ in its $$\hbox {NF}_{min}$$ characteristics. Linearity of the designed LNA is analysed in terms of third order input intercept point (IIP3) whose value is $$-\,4.22$$ dBm, when a two tone signal is applied at 6 GHz with a spacing of 10 MHz. The other important benefits of the proposed circuit are its group-delay variation and gain variation of $$\pm \,115\,\hbox {ps}$$ and $$\pm \,1.65\,\hbox {dB}$$ , respectively.

Design of Low Power UWB CMOS Low Noise Amplifier using Active Inductor for WLAN Receiver

This paper presents a low power Low Noise Amplifier (LNA) using 0.18µm CMOS technology for ultra wide band (UWB) applications. gm boosting common gate (CG) LNA is designed to improve the noise performance. For the reduction of on chip area, active inductor is employed at the input side of the designed LNA for input impedance matching. The proposed UWB LNA is designed using Advanced Design System (ADS) at UWB frequency of 3.1-10.6 GHz. Simulation results show that the gain of 10.74+ 0.01 dB, noise figure is 4.855 dB, input return loss <-13 dB and 12.5 mW power consumption.

A 3.0–10.0 GHz UWB Low-Noise Amplifier with Forward Body bias Technique

ABSTRACTAn ultra-wideband (UWB) low-noise amplifier (LNA) based on cascaded common source stage with shunt–shunt resistive feedback architecture is proposed. The wideband input impedance matching is accomplished by shunt–shunt resistive branch with inductor degeneration and parallel resistor-inductor-capacitor (RLC) load, forming two parallel RLC branches having inherently two wideband band-pass filter characteristics, resonating both at lower frequency and higher frequency. The output matching is achieved via a shunt inductor and a series resistor without the use of a buffer. Additionally, both series and shunt-inductive peaking techniques are employed in the proposed UWB LNA circuit design for bandwidth extension. To reduce the supply voltage headroom consumption, the forward body bias technique is also employed in the proposed topology. The resistor-capacitor (RC)-extracted results obtained in this paper are competitive in comparison with recent reported work in appreciating good noise figure (NF) performance as well as low-voltage headroom consumption. In the post-layout simulation results, the proposed complementary-metal-oxide-semiconductor (CMOS) UWB LNA dissipates only 13 mW while achieving the S11 below −11.4 dB, S22 below −11.7 dB, a flat S21 of 11.5 ± 0.6 dB, a maximum NF of 3.48 dB, within the range of 3.04 – 3.48 dB over the 3.0–10.0 GHz band of interest. Moreover, the IIP3 is within the range of −6.3 to −7.8 dBm, P1 dB of −14.7 to −16.8 as well as the K-factor of above 1 throughout the entire bandwidth operation, attesting the fact that the resistive feedback circuit is stable. The chip area consumption is approximated to 0.997 × 0.933 mm2.

A 0.6 V, low‐power and high‐gain ultra‐wideband low‐noise amplifier with forward‐body‐bias technique for low‐voltage operations

A two-stage common-source (CS) low-noise amplifier (LNA) that uses a forward-body-bias technique in N-type metal–oxide semiconductor devices and intended to achieve a high gain and low power consumption is proposed in this study for ultra-wideband (UWB) applications. Its first stage yields an exceptionally high gain because of high transconductance (gm1 = 16 mS) of the input device. It also shows simultaneous wideband input matching and low-noise figure (NF) characteristics with the aid of source degenerated inductors. A simple source degenerated CS topology with the shunt-peaking inductor Ld2 is designed as the second stage to enhance the gain response at high frequencies. Using a standard 90 nm complementary metal–oxide semiconductor process, the proposed UWB LNA achieves a gain S21 ≥ 20 dB in the frequency range of 3.1–10.6 GHz, while consuming only 12.6 mW power from a 0.6 V supply voltage. The simulation results show a minimum NF (NFmin) below 1.7 dB in the frequency range of 3.1–10.6 GHz and input return loss S11 < −10 dB in the frequency range of 3.5–10 GHz. When a two tone test is performed with a frequency spacing of 2 MHz, a high value of third-order input intercept point of −8 dBm is also achieved.

Design of low power CMOS ultra wide band low noise amplifier using noise canceling technique

This paper presents a design of a low power CMOS ultra-wideband (UWB) low noise amplifier (LNA) using a noise canceling technique with the TSMC 0.18μm RF CMOS process. The proposed UWB LNA employs a current-reused structure to decrease the total power consumption instead of using a cascade stage. This structure spends the same DC current for operating two transistors simultaneously. The stagger-tuning technique, which was reported to achieve gain flatness in the required frequency, was adopted to have low and high resonance frequency points over the entire bandwidth from 3.1 to 10.6GHz. The resonance points were set in 3GHz and 10GHz to provide enough gain flatness and return loss. In addition, the noise canceling technique was used to cancel the dominant noise source, which is generated by the first transistor. The simulation results show a flat gain (S21>10dB) with a good input impedance matching less than –10dB and a minimum noise figure of 2.9dB over the entire band. The proposed UWB LNA consumed 15.2mW from a 1.8V power supply.

인덕터 피킹기법을 이용한 초광대역 CMOS 저잡음 증폭기 설계

본 논문에서는 3.1-10.6GHz 초광대역 CMOS 저잡음 증폭기의 새로운 구조를 소개하였다. 제안된 초광대역 저잡음 증폭기는 입력 임피던스 정합에 RC 피드백과LC 필터회로를 사용하여 설계되었다. 이 설계에 전류 재사용 구조는 전력소비를 줄이기 위해 채택되었으며, 인덕터 피킹 기법은 대역폭을 확장하기 위하여 적용되었다. 이 초광대역 저잡음 증폭기의 특성을 <TEX>$0.18-{\mu}m$</TEX> CMOS 공정기술로 시뮬레이션을 수행한 결과는 3.1-10.6GHz 대역 내에서 전력이득은 14-14.9dB, 입력정합은 -10.8dB이하, 평탄도는 0.9dB, 잡음지수는 2.7-3.3dB인 것을 보여준다. 또한, 입력 IP3는 -5dBm이고, 소비전력은 12.5mW이다. In this paper, a new circuit topology of an ultra-wideband (UWB) 3.1-10.6GHz CMOS low noise amplifier is presented. The proposed UWB low noise amplifier is designed utilizing RC feedback and LC filter networks which can provide good input impedance matching. In this design, the current-reused topology is adopted to reduce the power consumption and the inductor-peaking technique is applied for the purpose of bandwidth extension. The performance results of this UWB low noise amplifier simulated in <TEX>$0.18-{\mu}m$</TEX> CMOS process technology exhibit a power gain of 14-14.9dB, an input matching of better than -10.8dB, gain flatness of 0.9dB, and a noise figure of 2.7-3.3dB in the frequency range of 3.1-10.6GHz. In addition, the input IP3 is -5dBm and the power consumption is 12.5mW.

A High Thermal Stability 3-10 GHz Low Noise Amplifier Using Current-reused Schematic with 0.5 ¼m pHEMT Technique

The objective of this article was to investigate if the ultra-wideband (UWB) low-noise amplifier (LNA) was modeled by utilizing a two-stage cascade circuit schematic, associated with the DC current-reused technique, which could improve the low power consumption in the 3.1–10.6 GHz frequency. The proposed UWB LNA amplifier was implemented with both the co-planer waveguide layout and 0.5-¼m GaAs Enhancement-mode pHEMT technology. Based on these technologies, this proposed UWB LNA, for which the chip size was shown to be 0.917 mm×0.816 mm, presented a flatness gain 3-dB bandwidth of 3.1-10.6 GHz, an excellent noise figure of 2.26–3.36 dB, a maximum power gain of 15.2 dB, and a power consumption of 17.7 mW, at 3 V power supply, respectively. Furthermore, the proposed UWB LNA was performed in the temperature stability measurement, for which stable characterizations of the S-parameters were obtained. Based on our experimental results, the low noise amplifier could obtain a wider band-width, low power consumption, and high flatness of gain in the 3.1–10.6 GHz frequency. Finally, the overall LNA characterization exhibited an ultra-wide bandwidth and low noise characterization, which illustrated that the proposed UWB LNA had a circuit compact size and exhibited favorable 3–10 GHz microwave characteristics.

Design of a 1~10 GHz High Gain Current Reused Low Noise Amplifier in 0.18 ㎛ CMOS Technology

In this paper, we propose a high gain, current reused ultra wideband (UWB) low noise amplifier (LNA) that uses TSMC 0.18 <TEX>${\mu}m$</TEX> CMOS technology. To satisfy the wide input matching and high voltage gain requirements with low power consumption, a resistive current reused technique is utilized in the first stage. A <TEX>${\pi}$</TEX>-type LC network is adopted in the second stage to achieve sufficient gain over the entire frequency band. The proposed UWB LNA has a voltage gain of 12.9~18.1 dB and a noise figure (NF) of 4.05~6.21 dB over the frequency band of interest (1~10 GHz). The total power consumption of the proposed UWB LNA is 10.1 mW from a 1.4 V supply voltage, and the chip area is <TEX>$0.95{\times}0.9$</TEX> mm.

3 - 10 GHz Ultra-Wideband Low-Noise Amplifier Using Inductive-Series Peaking Technique with Cascode Common-Source Circuit

The objective of this paper is to investigate a ultra-wideband (UWB) low noise amplifier (LNA) by utilizing a two-stage cascade circuit schematic associated with inductive-series peaking technique, which can improve the bandwidth in the 3-10 GHz microwave monolithic integrated circuit (MMIC). The proposed UWB LNA amplifier was implemented with both co-planer waveguide (CPW) layout and 0.15-μm GaAs D-mode pHEMT technology. Based on those technologies, this proposed UWB LNA with a chip size of 1.5 mm x 1.4 mm, obtained a flatness gain 3-dB bandwidth of 4 - 8 GHz, the constant gain of 4 dB, noise figure lower than 5 dB, and the return loss better than –8.5 dB. Based on our experimental results, the low noise amplifier using the inductive-series peaking technique can obtain a wider bandwidth, low power consumption and high flatness of gain in the 3 - 10 GHz. Finally, the overall LNA characterization exhibits ultra-wide bandwidth and low noise characterization, which illustrates that the proposed UWB LNA has a compact size and favorable RF characteristics. This UWB LNA circuit demonstrated the high RF characterization and could provide for the low noise micro-wave circuit applications.

Design and analysis of a compact ultra-wideband CMOS low-noise amplifier

In this letter, we proposed a low power, high gain, compact ultra-wideband (UWB) low noise amplifier (LNA) using TSMC 0.18-μm CMOS technology.To satisfy the wide input matching and high voltage gain requirements with low power consumption, a resistive current reused technique is utilized. The proposed UWB LNA has a voltage gain of 10.4–15.5 dB and a noise figure (NF) of 3.3–4.5 dB over the frequency band of interest (1–8 GHz). The total power consumption of the proposed UWB LNA is 10.4 mW from a 1.4 V supply voltage, and the chip area is 0.8 mm × 0.5 mm. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:345–348, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25747

A 0.18-μm CMOS UWB LNA Combined with High-Pass-Filter

An Ultra-WideBand(UWB) Low-Noise Amplifier(LNA) is proposed and is implemented in a 0.18-㎛ CMOS technology. The proposed UWB LNA provides excellent wideband characteristics by combining a High-Pass Filter (HPF) with a conventional resistive-loaded LNA topology. In the proposed UWB LNA, the bell-shaped gain curve of the overall amplifier is much less dependent on the frequency response of the HPF embedded in the input stage. In addition, the adoption of fewer on-chip inductors in the input matching network permits a lower noise figure and a smaller chip area. Measurement results show a power gain of +10 ㏈ and an input return loss of more than －9 ㏈ over 2.7 to 6.2 ㎓, a noise figure of 3.1 ㏈ at 3.6 ㎓ and 7.8 ㏈ at 6.2 ㎓, an input P1㏈ of －12 ㏈m, and an IIP3 of －0.2 ㏈m, while dissipating only 4.6 mA from a 1.8-V supply.

Low power consumption and high gain ultra‐wide‐band low noise amplifier

AbstractA low power consumption and high gain ultra‐wide‐band (UWB) low noise amplifier (LNA) utilizing a common‐gate stage connected with a common‐source stage by using current‐reused structure is proposed. The implemented LNA exhibits a maximum power gain of 14.2 dB with a total (core) power consumption of 7.2 mW (3.8 mW) under a 1.5 V power supply. A minimum noise figure of 4.1 dB was obtained within 3‐dB bandwidth of 2.7–8.2 GHz. The proposed UWB LNA presents the highest ratio of the power gain to power consumption among the compared papers. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 382–384, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24047

A 3.1–10.6 GHz Ultra-Wideband CMOS Low Noise Amplifier With Current-Reused Technique

A 3.1-10.6 GHz ultra-wideband (UWB) low noise amplifier (LNA) utilizing a current-reused technique and a simple high-pass input matching network is proposed. The implemented LNA presents a maximum power gain of 16dB, and a good input matching of 50Omega in the required band. An excellent noise figure (NF) of 3.1-6dB was obtained in the frequency range of 3.1-10.6GHz with a power dissipation of 11.9mW under a 1.8-V power supply. The proposed UWB LNA demonstrates the highest power gain and lowest NF among the published works in 0.18-mum CMOS technology

A novel CMOS low-noise amplifier design for 3.1- to 10.6-GHz ultra-wide-band wireless receivers

An ultra-wideband (UWB) 3.1- to 10.6-GHz low-noise amplifier (LNA) employing a common-gate stage for wideband input matching is presented in this paper. Designed in a commercial 0.18-mum 1.8-V standard RFCMOS technology, the proposed UWB LNA achieves fully on-chip circuit implementation, contributing to the realization of a single-chip CMOS UWB receiver. The proposed UWB LNA achieves 16.7plusmn0.8 dB power gain with a good input match (S11<-9 dB) over the 7500-MHz bandwidth (from 3.1 GHz to 10.6 GHz), and an average noise figure of 4.0 dB, while drawing 18.4-mA dc biasing current from the 1.8-V power supply. A gain control mechanism is also introduced for the first time in the proposed design by varying the biasing current of the gain stage without influencing the other figures of merit of the circuit so as to accommodate the UWB LNA in various UWB wireless transmission systems with different link budgets

1.8‐V 3.1–10.6‐GHz CMOS low‐noise amplifier for ultra‐wideband applications

AbstractA novel CMOS low‐noise amplifier (LNA) for 3.1–10.6‐GHz ultra‐wideband (UWB) applications is presented in this paper. As opposed to most of the previously reported UWB LNAs, which are based on SiGe technology, the proposed UWB LNA is designed based on chartered semiconductor manufacturing (CSM) 0.18‐μm 1.8‐V standard RFCMOS technology. The prelayout and post‐layout circuit simulation results show that low noise figure, good input and output matching, a relatively flat gain in the 3.1–10.6‐GHz UWB band, and low power consumption features are all achieved in the proposed CMOS UWB LNA. © 2005 Wiley Periodicals, Inc. Microwave Opt Technol Lett 44: 299–302, 2005; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.20616