Proposed Single-pole Double-throw Switch Research Articles

High isolation of SPDT PIN diode switch using switchable dumbbell-shaped DGS in millimeter wave 28 GHz band

This paper proposes a high isolation of single pole double throw (SPDT) PIN diode switch using switchable dumbbell-shaped defected ground structure (DGS). The proposed SPDT switch was designed for radio frequency (RF) front-end transceiver of antenna array multiple input multiple output (MIMO) in millimeter wave 28 GHz band. The switchable dumbbell-shaped DGS can be switched between allpass and bandstop responses where the bandstop response of the DGS can be utilized as a high isolation in the SPDT PIN diode switch circuit. A simple mathematical analysis is explained in this paper for the bandstop and allpass responses of the switchable dumbbell-shaped DGS. The propose SPDT switch was designed based on Roger RT/Duroid 5880 with 0.254 mm thickness and relative dielectric constant of 2.2. The simulated result showed that the proposed SPDT PIN diode switch produced an isolation of 36.36 dB at 27.3 GHz (center of 28 GHz band), which was 63% higher than the conventional SPDT design.

An Ultra-Wideband, High Power and High Isolation Single-Pole-Double-Throw Switch Using Capacitive Loading Approach

This paper presents an ultra-wideband, series-shunt type single-pole-double-throw (SPDT) switch with high isolation and good power handling capability from DC to 40 GHz. A new topology using capacitive loading on the shunt arms was proposed to improve the isolation across the entire band. The effect of the capacitive loading has been theoretically analyzed. Using the simple SPDT topology with one shunt arm as comparison, the capacitive loading approach exhibited an improvement of 5.9 dB in isolation at 40 GHz. To enhance the power handling capability, the stacked-FET configuration was adopted at the shunt arms. The optimum design has been implemented in the commercially available 0.15-lm GaAs pseudomorphic high-electron-mobility transistor (pHEMT) process and demonstrated an insertion loss of less than 3 dB, an isolation of greater than 39 dB, and an input 1-dB compression point (P1dB) of better than 32 dBm from DC to 40 GHz. To our knowledge, the proposed SPDT switch demonstrates the highest isolation over the widest bandwidth among other reported works to date.

High-Powered RF SOI Switch With Fast Switching Time for TDD Mobile Applications

This paper presents a fast switching and high-powered single-pole double-throw (SPDT) switch for RF switch circuits, such as TRx antenna switches and frequency band (or operation mode) selection switches in mobile handset applications. For fast switching time and performances of the RF switch, we proposed a novel method that can “selectively” control the impedance of a gate biasing circuit (“high” or “low” impedance). The proposed SPDT switch use the low impedance of the gate biasing circuit for fast switching time and use the high impedance of the gate biasing circuit to avoid the degradation of the insertion loss and harmonics. The proposed SPDT switch has no additional bias and no large payment for size consumption. According to measurement results, the turn-on switching time of the proposed SPDT switch was <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.35~\mu \text{s}$ </tex-math></inline-formula> (at 2 GHz). The insertion loss, isolation, and return loss at 2 GHz were 0.16 dB, 47.1 dB, and 24 dB respectively. 2nd and 3rd harmonic levels at 25 dBm input power at 2 GHz were −88.7 dBm and −78.9 dBm, respectively. Power handling capability was 39.5 dBm of input power at 2 GHz. The designed SPDT switch was implemented in a 0.13- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> partially depleted silicon-on-insulator (PD-SOI) process.

Design of a K-Band High-Linearity Asymmetric SPDT CMOS Switch Using a Stacked Transistor

This study presents a high-linearity K - band single-pole double-throw (SPDT) switch with asymmetric topology in a 65-nm CMOS process for 5G applications. To simultaneously obtain high power-handling capability and high isolation in the Tx and Rx modes, respectively, we propose an SPDT switch using asymmetric topology and the stacked-transistor technique. In both the Tx/Rx modes, the proposed SPDT switch operates with an insertion loss of less than 2.1 dB and isolation better than 22.5 dB in the frequency range 20–25 GHz. At 22 GHz, the measurement results of the input 1-dB compression point (IP1 dB) are 32.5 and 4.7 dBm in Tx and Rx modes, respectively. The chip core size of the proposed SPDT switch is 0.03 mm2.

SPDT discrete switch design using switchable SIW resonators for millimeter wave MIMO transceiver

A single pole double throw (SPDT) discrete switch design using switchable substrate integrated waveguide (SIW) resonators is proposed in this paper. It was designed for the millimeter wave multiple input multiple output (MIMO) transceiver. An example application is for 5G communication in 26 GHz band. High isolation between transmitter and receiver (in the transceiver) is needed in SPDT switch design to minimize any high radio frequency (RF) power leakage in the receiver. Therefore, the use of switchable SIW resonators can achieve higher isolation if compared to the conventional series SPDT switch, where the isolation of the proposed SPDT is depend on the bandstop response of the SIW resonators. The switchable SIW resonators can be switched between allpass and bandstop responses to allow the operation between transmit and receive modes. As a result, the simulation and measurement showed that the proposed SPDT switch produced an isolation higher than 25 dB from 24.25 to 27.5 GHz compared to the conventional design.

Design of high‐isolation and low‐loss single pole double throw switch based on the triple‐coupled transformer for ultra‐wideband phased array systems

AbstractThis paper proposes a single pole double throw (SPDT) switch based on the triple‐coupled transformer. The triple‐coupled transformer utilizes a novel structure with three stacked coupled inductors which are placed in nonconcentric positions to ensure the isolation of SPDT switch. The SPDT switch obtains additional optimization space to improve insertion loss performance under the premise of reassuring isolation. The equivalent circuit model is built to interpret the mechanism of the SPDT switch and transformer. The proposed switch is implemented with the 65‐nm CMOS process, the simulated results show the isolation between input‐to‐output ports are better than 25 dB at 24–38 GHz. The proposed SPDT switch achieves a minimum insertion loss of 1.56 dB with compact chip size 625 × 370 μm2 (with PADs).

Low-Mismatch and Low-Loss Transformer-Based SPDT Switch with Switching Load Technique for 5G Applications

This paper proposes a switching load technique to improve the mismatch at outputs of the transformer-based single pole double throw (SPDT) switch, thus improving the insertion loss (IL) performance. A switch is introduced as the load of the primary inductor of the conventional transformer-based SPDT switch to improve the IL performance in transmission and receiving operation modes. A transformer-based SPDT switch is implemented with the switching load technique in TSMC 40[Formula: see text]nm CMOS technology. The transformer which has a symmetrical shape is implemented with the thick metal for low IL propose. The simulated results show that the proposed SPDT switch achieves a minimum insertion loss of 1.64[Formula: see text]dB and the IL is better than 2.2[Formula: see text]dB across the range from 24 to 35[Formula: see text]GHz. The proposed SPDT switch occupies a core area of [Formula: see text]m2and the return losses are better than [Formula: see text][Formula: see text]dB at 24–35[Formula: see text]GHz.

A Small-Size K-Band SPDT Switch Using Alternate CMOS Structure With Resonating Inductor Matching

A single-pole double-throw (SPDT) CMOS switch at 15–25 GHz is presented, which has a small size, low insertion losses, and high-power handling capabilities for both output nodes. It has an SPDT structure in which nMOS and pMOS are alternately used as series and shunt transistors. An inductor-matching network is placed between two output nodes for input and output matching, which is also used to increase isolation by resonating out the off capacitances. The proposed SPDT switch is fabricated using a 28-nm CMOS process. It achieves an insertion loss of less than 1.9 dB from 15 to 25 GHz. The measured IP0.2dB of two outputs is 17.4 and 18.3 dBm, respectively. It has an isolation of 25 dB at 20 GHz. The measured ON/OFF switching time is less than 2.3 ns. The proposed SPDT switch has a core area of only 0.02 mm2.

Miniaturized, Ultra-Wideband and High Isolation Single Pole Double Throw Switch by Using π-Type Topology in GaAs pHEMT Technology

In this brief, a compact ultra-wideband monolithic microwave integrated circuit single pole double throw (SPDT) switch with high isolation level and low insertion loss is presented. A ${\pi }$ -type topology, consisted of a transmission line with an electrical length of less than 90° and two parallel grounded metal-insulator-metal capacitors, is employed to replace the conventional $\lambda $ /4 transmission line between the adjacent parallel field effect transistors of the serial parallel SPDT switch. In comparison with the traditional method, an ultra-wideband high isolation behavior and the reduced dimension is achieved simultaneously with the proposed SPDT switch. Furthermore, the equivalent circuit model is built to interpret the mechanism of the improved technique. A chip sample is fabricated with Gallium Arsenide processing with a size of $1.25\times 1.05$ mm2. The measured insertion loss is less than 1.9 dB and the isolation is better than 36 dB from DC to 30 GHz. Good agreements are observed between the simulated and measured results.

40 dB-Isolation, 1.85 dB-Insertion Loss Full CMOS SPDT Switch with Body-Floating Technique and Ultra-Small Active Matching Network Using On-Chip Solenoid Inductor for BLE Applications

In the IoT/wearable devices, the antenna is shared with the receiver and transmitter of the transceiver. This requires the control of the switch between the antenna and the control circuitry to achieve both low insertion loss and high isolation. This paper presents a low insertion loss and high isolation switch based on Single Pole Double Throw (SPDT) switch for 2.4 GHz Bluetooth low power (BLE) transceiver. The body-floating technique is used to improve the insertion loss’s performance. An ultra-small on-chip matching network with high Q-factor is proposed. The shunt transistors are used as active shunt capacitors that create the active matching network to improve isolation characteristics. The proposed SDPT switch was designed using 55 nm CMOS process with the total area of 110 μm × 210 μm. The insertion loss and isolation characteristics of the proposed SPDT switch observed at 2.4 GHz are 1.85 dB and 40 dB, respectively.

Compact 35–70 GHz SPDT Switch With High Isolation for High Power Application

This letter proposes a broadband high isolation and high power compact single pole double throw (SPDT) switch. In contrast to the traditional structure of grounded source pad, the source pad of the shunt-stacked FET is absorbed into the transmission line, and the drain of the shunt-stacked FET is grounded to a via-hole. This structure helps to extend the operation bandwidth and reduce the chip size. The proposed SPDT switch is composed of six shunt-stacked FET units on each branch with this novel structure. Stacked FETs technique increases the voltage handling by placing two FETs in series. It has been fabricated using a commercial $0.1~\boldsymbol {\mu }\text{m}$ GaAs pseudomorphic high-electron-mobility transistor (PHEMT) process. The chip size is $1.2\times 0.8$ mm2. The switch operates at the frequency range of 35–70 GHz with less than 3 dB insertion loss and more than 40-dB isolation. The switch demonstrates a 1 dB insertion loss compression with a 20.2 dBm input power at 31 GHz. The isolation is larger than 30 dB from 10 to 95 GHz. To the best of the authors’ knowledge, this broadband isolation performance is among the best of the reported SPDT switches.

A Quasi-Elliptic Bandpass Filter-Integrated Single-Pole Double-Throw Switch

Abstract This paper proposes a quasi-elliptic bandpass filter-integrated single-pole double-throw (SPDT) switch. The series-parallel configuration of p-i-n diodes embedded into the impedance matching circuit is proposed to combine two quasi-elliptic response bandpass filters to constitute the proposed SPDT switch. To validate our design approach, a proposed quasi-elliptic bandpass filter-integrated SPDT switch is designed and fabricated with a central frequency of 1.25 GHz and a 3 dB fractional bandwidth of 16 %. Low insertion loss in the on state and good isolation in the off state are achieved. The switch size including bias circuits but excluding feeding lines is 0.447λg×0.134λg.

Substrate-Integrated-Waveguide (SIW) Single-Pole-Double-Throw (SPDT) Switch for X-Band Applications

A substrate-integrated-waveguide (SIW) single-pole double-throw (SPDT) switch is presented for X-band applications. Inductive posts with rectangular slots are embedded in the SIW to control the traveling EM wave. By adding PIN diodes on the top slots of the inductive posts, we achieved the ability to switch in the SIW technology; then, an SIW SPDT switch was designed. The proposed SPDT switch has a measured isolation (S31) of greater than 10 dB, isolation (S32) of greater than 15 dB, and an insertion loss (IL) of less than 2.55 dB, from 8.24-10.36 GHz.

Analysis and Design of 60-GHz SPDT Switch in 130-nm CMOS

This paper proposes a new 60-GHz single-pole-double-throw (SPDT) switch. It is designed in a 1.2-V 130-nm bulk CMOS and has a small core area of 222 μm × 92 μm. The switch exhibits measured insertion loss of 1.7 dB, isolation of 22 dB, input return loss of 20 dB, output return loss of 14 dB, and simulated power-handling capability of 13.8 dBm at 60 GHz. The proposed SPDT switch demonstrates such superior performances and consumes a much smaller die area to those of other SPDT switches, and therefore has potential to be used in highly integrated 60-GHz CMOS radios.

Design and fabrication of a single membrane push-pull SPDT RF MEMS switch operated by electromagnetic actuation and electrostatic hold

In this paper, we report a new push-pull-type SPDT (single pole double throw) switch actuated by the combination of electromagnetic and electrostatic forces for low power and low voltage operation. The switch is initially actuated by large electromagnetic force to change its state and is held to maintain its state by applying electrostatic force to reduce static power consumption. The electromagnetic force can be easily generated at low voltage. The maximum actuation voltage is below 4.3 V and the required energy is 15.4 µJ per switching. It achieves signal isolation of −54 dB and insertion loss of −0.16 dB at 2 GHz, respectively. For 20 GHz operation, isolation and insertion loss were measured as −36 dB and −0.52 dB, respectively. The proposed SPDT switch combines two switching elements in a single structure, simplifying the overall structure and control signals and eliminating mismatches between the two switching elements. The dimension of the switch has been optimized using FEM simulation and analytical calculations. We have successfully carried out a lifetime test over more than 166 million cycles with the maximum actuation voltage below 4.3 V.