Proposed Scheduling Technique Research Articles

Modified WRR Scheduling Algorithm for WiMAX Networks

Worldwide Interoperability for Microwave Access (WiMAX), which is also known as 802.16 standard, supports last-mile broadband access wireless networks. WiMAX has many advantages including wide coverage area and high bandwidth. These advantages enable WiMAX to support long transmission range and high data rate compared to cellular and WiFi network. WiMAX technology uses a number of scheduling techniques in the Medium Access Control (MAC) layer, which is responsible for the utilization of available resources in the networks and distribute them among users in order to ensure the desired quality of service. In this study, we propose a Modified Weighted Round Robin (MWRR) scheduler in order to decrease the average end-to-end delay and improve the average throughput. The proposed scheduling technique has been designed and simulated using the QualNet 5.0.2 network simulator. In order to evaluate the performance of our proposed approach, we compared our results to the results of well-known scheduling techniques (weighted Round Robin (WRR), Strict Priority (SP), and Weighted Fair Queuing (WFQ)). The average percentage of improvement was around 4%.

Mapping Parameterized Cyclo-static Dataflow Graphs onto Configurable Hardware

In recent years, parameterized dataflow has evolved as a useful framework for modeling synchronous and cyclo-static graphs in which arbitrary parameters can be changed dynamically. Parameterized dataflow has proven to have significant expressive power for managing dynamics of DSP applications in important ways. However, efficient hardware synthesis techniques for parameterized dataflow representations are lacking. This paper addresses this void; specifically, the paper investigates efficient field programmable gate array (FPGA)-based implementation of parameterized cyclo-static dataflow (PCSDF) graphs. We develop a scheduling technique for throughput-constrained minimization of dataflow buffering requirements when mapping PCSDF representations of DSP applications onto FPGAs. The proposed scheduling technique is integrated with an existing formal schedule model, called the generalized schedule tree, to reduce schedule cost. To demonstrate our new, hardware-oriented PCSDF scheduling technique, we have designed a real-time base station emulator prototype based on a subset of long-term evolution (LTE), which is a key cellular standard.

Enhancing the Performance of Feedback Scheduling

Feedback scheduling is a kind of process scheduling mechanism where process doesn’t come with any priority. According to the CPU burst needed by the process and the CPU burst remaining the processes are shifted between queues of the feedback scheduler to get completed. In multilevel feedback queue the total architecture is divided into multiple prioritised queues. In this paper, we give an approach for jobs which starve in the lower priority queue for long time to get CPU cycle. As a result response time of those starved processes decreases eight to ten percent and over all turn around time of the whole scheduling process decreases around eight to ten percents. In comparison to other types of MLFQs the performance of the proposed scheduling technique is better and practical according to the consequence.

Windows NT상에서의 OPRoS 컴포넌트 스케줄러의 실시간성 분석 및 개선

The OPRoS (Open Platform for Robotic Service) framework provides uniform operating environment for service robots. As an OPRoS-based service robot has to support real-time as well as non-real-time applications, application of Windows NT kernel based operating system can be restrictive. On the other hand, various benefits such as rich library and device support and abundant developer pool can be enjoyed when service robots are built on Windows NT. The paper presents a user-mode component scheduler of OPRoS, which can provide near real-time scheduling service on Windows NT based on the restricted real-time features of Windows NT kernel. The component scheduler thread with the highest real-time priority in Windows NT system acquires CPU control. And then the component scheduler suspends and resumes each periodic component executors based on its priority and precedence dependency so that the component executors are scheduled in the preemptive manner. We show experiment analysis on the performance limitations of the proposed scheduling technique. The analysis and experimental results show that the proposed scheduler guarantees highly reliable timing down to the resolution of 10ms.

AUTOSAR기반 EPS 시스템 소프트웨어 컴포넌트의 스케줄링 설계 및 시뮬레이션

Through the AUTOSAR methodology, the embedded software shall become more flexible, reusable, maintainable than ever. However, it is not mentioned about specific timing constraints of software components in AUTOSAR. There are a few basic principles for mapping runnable entities. At this point, AUTOSAR software design with optimal scheduling method is one of the enabling technologies in vehicle embedded system. This paper presents an approach based on mapping runnable entities and task scheduling design method for EPS (Electric Power Steering) software components, based on AUTOSAR. In addition, the experimental results of concurrent simulation show that the proposed scheduling technique and timing synchronization in the software component design can achieve the improved torque ripple performance and it well suited for EPS application software.

Scheduling of Demand Side Resources Using Binary Particle Swarm Optimization

Interruptible loads represent highly valuable demand side resources within the electricity industry. However, maximizing their potential value in terms of system security and scheduling is a considerable challenge because of their widely varying and potentially complex operational characteristics. This paper investigates the use of binary particle swarm optimization (BPSO) to schedule a significant number of varied interruptible loads over 16 h. The scheduling objective is to achieve a system requirement of total hourly curtailments while satisfying the operational constraints of the available interruptible loads, minimizing the total payment to them and minimizing the frequency of interruptions imposed upon them. This multiobjective optimization problem was simplified by using a single aggregate objective function. The BPSO algorithm proved capable of achieving near-optimal solutions in manageable computational time-frames for this relatively complex, nonlinear and noncontinuous problem. The effectiveness of the approach was further improved by dividing the swarm into several subswarms. The proposed scheduling technique demonstrated useful performance for a relatively challenging scheduling task, and would seem to offer some potential advantages in scheduling significant numbers of widely varied and technically complex interruptible loads.

Feedback scheduling of computing resources based on support vector machines

The computing resource is generally resources-limited in the real-time control systems(RTCS).Due to the uncertain running conditions and dynamic fluctuation of workload,the system always runs in an unexpected open environment.A feedback scheduling technique of computing resources based on support vector machines(SVM) was designed in order to ensure the system's stable running.The feedback scheduler of the system,which monitored the system's computing resources periodically,predicted a next sampling period for each control task by using SVM mechanism.Consequently,the computing resources of the system can be dynamically allocated online.The simulation of results highlights that the proposed scheduling technique is more effective in comparison with ideal case and traditional open-loop scheduling techniques.

Server-based execution of periodic tasks on dynamically reconfigurable hardware

A prototype system that executes a set of periodic real-time tasks utilising dynamic hardware reconfiguration is presented. The proposed scheduling technique, merge server distribute load (MSDL), is not only able to give an offline guarantee for the feasibility of the task set, but also minimises the number of device configurations. After describing this technique, the schedulability analysis is extended to cover different runtime system overheads, including the device reconfiguration time. Then, a light-weight runtime system that performs the online part of the MSDL scheduling technique is detailed. The runtime system is implemented entirely in hardware. Finally, the corresponding synthesis tool flow is outlined and the overhead posed by the runtime system is reported.

A FAST SCHEDULING ALGORITHM FOR LOW POWER DESIGN

In this paper, a fast low power scheduling algorithm is presented for high-level synthesis with multiple voltages. The resources are assumed to operate at different voltages and their power consumption and delay for each voltage level is known in advance. The proposed methodology achieves maximal power reduction of functional units by identifying the maximal available parallelism of power hungry operators in an initial schedule. The proposed methodology is developed in the framework of a modified stochastic evolution mechanism in order to tame the computational complexity. The proposed scheduling technique is extremely fast and it runs in quadratic complexity in the number of the nodes in the data flow graph of the design. This is the fastest reported time of scheduling algorithms for resource-and-latency constrained scheduling with resources operating at multiple voltages. The algorithm produces results within accuracy of 3%–5% of the linear programming method.

A methodology for low power scheduling with resources operating at multiple voltages

This work addresses the problem of low power design in high-level synthesis in the scenario of the resources operating at multiple voltages. The problem of resource-and-latency constrained scheduling is tackled and a novel methodology for scheduling as well as design space exploration is proposed. The proposed methodology achieves maximal power reduction of functional units by identifying the maximal parallelism of power hungry operators in resource-constrained/time-constrained designs. A novel scheme is devised for recognizing the “zones” of parallel operators that result in maximal power savings when rescheduled to lower voltages. The proposed methodology is developed in the framework of a modified stochastic evolution mechanism in order to tame the computational complexity. The proposed scheduling technique is extremely fast and it runs in O( n 2), where n is the number of the nodes in the data flow graph of the design. This is the fastest reported time of scheduling algorithms for resource-and-latency constrained scheduling with resources operating at multiple voltages. The algorithm produces results within accuracy of 3–5% of the integer-linear-programming based (i.e., exponential-time-complexity) method. The details and the analysis of the results on the standard high-level synthesis benchmarks are provided. Further, analysis of schedules is given for considering generation of control signals for switching the resources. This is the first work to consider such analysis besides proposing an efficient algorithm.

A Genetic-Algorithm Approach to Scheduling Communications for Embedded Parallel Space–Time Adaptive Processing Algorithms

Computational efficiency is of great significance for high-performance embedded applications. The work here develops and evaluates a genetic-algorithm-based (GA-based) optimization technique for the scheduling of messages for a class of parallel embedded signal processing techniques known as space–time adaptive processing (STAP). The GA-based optimization is performed off-line, resulting in static schedules for the compute nodes of the parallel system. These static schedules are utilized for the on-line implementation of the parallel STAP application. The primary motivation and justification for devoting significant off-line effort to solving the formulated scheduling problem is the resulting reduction of hardware resources required for the actual on-line implementation. Numerical studies illustrate that reductions in hardware requirements of around 50% can be achieved by employing the results of the proposed scheduling techniques. This reduction in hardware requirement is of critical importance for STAP, which is typically an airborne application in which the size, weight, and power consumption of the computational platform are severely constrained.

Compile-time scheduling of dynamic constructs in dataflow program graphs

Scheduling dataflow graphs onto processors consists of assigning actors to processors, ordering their execution within the processors, and specifying their firing time. While all scheduling decisions can be made at runtime, the overhead is excessive for most real systems. To reduce this overhead, compile-time decisions can be made for assigning and/or ordering actors on processors. Compile-time decisions are based on known profiles available for each actor at compile time. The profile of an actor is the information necessary for scheduling, such as the execution time and the communication patterns. However, a dynamic construct within a macro actor, such as a conditional and a data-dependent iteration, makes the profile of the actor unpredictable at compile time. For those constructs, we propose to assume some profile at compile-time and define a cost to be minimized when deciding on the profile under the assumption that the runtime statistics are available at compile-time. Our decisions on the profiles of dynamic constructs are shown to be optimal under some bold assumptions, and expected to be near-optimal in most cases. The proposed scheduling technique has been implemented as one of the rapid prototyping facilities in Ptolemy. This paper presents the preliminary results on the performance with synthetic examples.