Proposed Protection Circuit Research Articles

Improved Gate-Voltage-Driven Desaturation Short-Circuit Protection Circuit With Robust Switching Noise Immunity for WBG Power Semiconductors

Wide bandgap (WBG) power semiconductors are used in numerous power conversion applications because of their excellent switching characteristics. However, it is difficult to ensure short-circuit protection for WBG power semiconductors because of their shorter short-circuit withstand time. The fast-switching characteristics of WBG power semiconductors induces severe fluctuations in the drain-source voltage and drain current in switching transients, which results in the false triggering of the protection circuit. Therefore, the fast response speed and switching noise suppression are key requirements of the protection circuit for a WBG power semiconductor. To meet these requirements, an improved gate-voltage-driven desaturation protection circuit with a fast response speed and robust noise immunity is proposed in this study. The effect of switching noise on the proposed protection circuit is analyzed, and a detailed design procedure based on the analysis results is provided. The experimental results indicate that the protection delay of the proposed circuit is within 91 ns; additionally, the proposed circuit can survive switching noise during normal operation. Finally, the noise immunity analysis results are verified through experiments under various protection circuit parameter sets.

A short circuit protection circuit for SiC MOSFET with self-adjustive blanking time

This paper proposed a desaturation (DESAT) short circuit (SC) protection circuit for SiC MOSFET, where a blanking time setting module and an SC detection module are designed. The fall time of the drain-source voltage (VDS) for each switching period of SiC MOSFET is recorded and set as the blanking time for the hard switching fault (HSF) detection in the next switching period. Consequently, the detection delay for HSF is self-adjustive and can respond quickly to the operating state of SiC MOSFET. FPGA and discrete components are used to implement the proposed circuit. The function of the proposed circuit is verified using the double pulse test. The experiment results show that the blanking time automatically increases with the increase of load current. The default detection delay of the proposed protection circuit is set 240ns for HSF and can be adjusted during the subsequent switching period. So in the test under a 400V bus voltage, the detection delay is 240ns for HSF at the first switching period. And for HSF occurs at the second switching period, the detection delay is 200ns adjusted according to the operating state of the first switching period. Meanwhile, the detection delay for fault under load (FUL) is 72ns.

Improved Rotor Braking Protection Circuit and Self-Adaptive Control for DFIG during Grid Fault

This paper introduces an improved rotor braking protection circuit configuration and the corresponding self-adaptive control strategy to enhance the low voltage ride-through (LVRT) capability of the doubly-fed induction generator (DFIG). The proposed protection circuit consists of a crowbar circuit and a series rotor braking resistor array, which guarantees the safe operation of wind generators under the LVRT. Moreover, to adapt the proposed protection and further enhance the performance of the improved configuration, a corresponding self-adaptive control strategy is presented, which regulates the rotor braking resistor and protection exiting time automatically through calculating the rotor current in the fault period. The LVRT capability and transient performance of the DFIG by using the proposed method is tested with simulation. Compared with the conventional crowbar protection or the fixed rotor braking protection, the proposed protection and the control strategy present several advantages, such as retaining the control of the rotor side converter, avoiding repeated operation of the protection and accelerating the damping of stator flux linkage during a grid fault.

An Instantaneously Triggered Short-Circuit Protection Architecture for Boost Switching DC/DC Converters

This paper presents a protection circuit architecture that helps us to reduce the chances of damages in a boost switching converter due to fault conditions of output short-to-ground or power-switch short-circuits. Those two short-circuit faults can cause the inductor current to run away and result in damages. The proposed protection circuit can detect those two fault conditions within a few microseconds and then isolate the converter from its power supply. The fault detection is implemented by sensing the voltage drop across the primary inductor in a 1:1 coupled transformer which replaces the single-winding inductor in a boost converter. If a short-circuit fault happens at either the output load or at the power switch, the secondary inductor will shoot current to turn off a pass PMOSFET, which disconnects the primary inductor from the input supply. The protection circuit was built on the top of a commercial boost converter and was verified under short-circuit faults over a wide load current range. The proposed protection structure effectively reduced the inductor current overshoot during short-circuit event at the expenses of 1.2% drop of the peak efficiency during normal operation.

Balanced Power Amplifier Protection Against Load Mismatch

This letter presents a new approach for balanced power amplifier protection against load mismatch under pulsed-RF operation. The proposed protection mechanism completely eliminates the reflected power under severe mismatch conditions while not affecting nominal operating condition. The concept is based on detection, comparison, and switching technique. The proposed protection circuit offers full protection against open and short at the output. This protection mechanism has been demonstrated on a 10-W $X$ -band power amplifier, intended to be used in space borne radar payloads. The reaction time of the proposed protection mechanism is <100 ns.

Parallel R-L configuration crowbar with series R-L circuit protection for LVRT strategy of DFIG under transient-state

This paper proposes an impedance protection circuit configuration to enhance the ride-through of doubly-fed induction generators (DFIGs) based wind turbines (WTs) during faults. The proposed impedance protection circuit configuration comprises of a parallel R-L impedance crowbar and a series R-L impedance circuit. Traditionally, resistive-crowbar (i.e., R-crowbar) circuit is applied as the means of protection for the DFIG WT which efficiently protects the rotor-side converter (RSC) and dc-link capacitor against the effects of severe grid faults. However, the conventional R-crowbar circuit disconnects the RSC leading to the loss of generator excitation control. During that time, the WT generator becomes a conventional squirrel-cage induction generator (SCIG) which obtains its magnetization current from the point of common coupling (PCC) via stator winding terminals. This phenomenon further deepens the voltage-dip at the PCC. Alternatively, integrating the R-crowbar with series R-L branch partially maintains the RSC connection to the rotor winding. Hence the generator excitation control is also partially maintained but oscillations of the rotor currents and dc-link voltage can still affect the ride-through performances of WT driven by the DFIG. With the proposed protection circuit configuration, it compensates the deficiency of the two conventional protection circuits configuration. In order to validate the performance of the proposed scheme, extensive simulation studies are carried out using MATLAB/Simulink software. From the comparative simulation results, improved performances of the DFIG under transient-state are achieved with the proposed protection circuit configuration than the conventional protection circuits.

Design of fabrication of ESD protection circuit with high holding voltage for power IC

ABSTRACTIn this paper, A newly Silicon Controlled Rectifier (SCR)-based Electric Static Discharge (ESD) protection circuit is proposed. The proposed circuit has the latch-up immunity in normal operating conditions with the high holding voltage by inserting the floating regions. To verify the electrical characteristics, a Technology Computer Aided Design (TCAD) simulation is performed by setting each of variables: D1, D2, D3, and D4. The results of the simulation show that the proposed protection circuit has the holding voltage 5 V higher than the conventional circuits and has the same level of robustness properties as the existing SCR. In addition, the proposed circuit is fabricated through a 0.18 μm Bipolar-CMOS-DMOS process. The electrical characteristics are confirmed by measuring Transmission Line Pulse, and the robustness properties are measured through Human Body Model (HBM) and Machine Model (MM). The holding voltage is about 20 V, which has the increases above 18 V or more compared to the conventional SCR. Therefore, the proposed circuit is proved to have the better ESD protection performance than HBM 8 kV and MM 800 V higher than HBM 2 kV and MM 200 V, the commercial standard.

Effective protection for doubly fed induction generator-based wind turbines under three-phase fault conditions

This paper proposes an effective protection strategy which combines three-crowbar circuit configuration (TCCC), a small bypass resistor (SBR) for wind turbines (WTs) based on the doubly fed induction generators (DFIGs). The TCCC includes (i) resistive crowbar, (ii) inductive crowbar, and (iii) capacitive crowbar. Conventionally, applying only resistive-crowbar circuit as the only means of protection on the DFIG WT, the rotor-side power converter (RSPC) and dc-link capacitor are protected against the effects of a severe voltage dip. However, tripping the RSPC leads to loss of excitation control, and the DFIG behaves like the squirrel-cage induction generator which obtains its magnetization current from the grid which further deepen the terminal voltage. Moreover, integrating the resistive crowbar with series R–L branch keeps the RSPC connection active, but the generator excitation control is partially retained and the oscillations of the rotor currents and dc-link voltage can heavily deteriorate the performance of the generator. Thus, the TCCC-SBR circuit is proposed to compensate for the deficiency when the two conventional circuits are applied. Its performance validation is performed via extensive simulation studies using MATLAB/Simulink software. From the comparative simulation results, more improved fault ride-through capability of the DFIG is achieved with the proposed protection circuit than the conventional protection circuits.

The Analysis of SCR-Based ESD Protection Circuit with P-Drift and N+ Floating Region

In this paper, a novel SCR (Silicon Controlled Rectifier)-based ESD(Electrostatic Discharge) protection circuit for power clamp is proposed. The proposed protection circuit has high holding voltage due to floating n+ region which reduces current gain of parasitic bipolar transistor. This characteristic makes it ensure latch-up immunity. The electrical characteristics of the proposed ESD protection circuit have been simulated by using Synopsys TCAD simulation tool. According to the simulation results, the proposed protection circuit has high holding voltage of about 4.61V to 8.75V as design variation. Also, it is verified by using TLP (Transmission Line Pulse) system. As a result of measurement, it has holding voltage of 15.7V to 19.35V as design variation and high robustness above HBM 6kV, MM 600V.

Снижение длины &amp;#34;мертвой&amp;#34; зоны защиты асинхронного двигателя в случае обрыва фазы питающей сети при использовании блока защиты УБЗ-301

Shows the proposed protection circuit reverse-phase induction motor with a protective device UBZ-301, which allows to reduce the &amp;#34;dead&amp;#34; zone of protection for loss of one phase mains preserving function “Control of phase sequence”.

A single lithium-ion battery protection circuit with high reliability and low power consumption

A single lithium-ion battery protection circuit with high reliability and low power consumption is proposed. The protection circuit has high reliability because the voltage and current of the battery are controlled in a safe range. The protection circuit can immediately activate a protective function when the voltage and current of the battery are beyond the safe range. In order to reduce the circuit's power consumption, a sleep state control circuit is developed. Additionally, the output frequency of the ring oscillation can be adjusted continuously and precisely by the charging capacitors and the constant-current source. The proposed protection circuit is fabricated in a 0.5 μm mixed-signal CMOS process. The measured reference voltage is 1.19 V, the overvoltage is 4.2 V and the undervoltage is 2.2 V. The total power is about 9 μW.

An Application of a Physics-based IGBT Model to a Protection Circuit for Short-Circuit Conditions

This paper presents a protection circuit for a fault under load (FUL). The protection circuit is characterized by the reverse transfer capacitance characteristic of IGBTs. The reverse transfer capacitance depends on the collector-emitter voltage and has a significant influence on the switching behavior under short-circuit conditions and normal conditions. An FUL is detected by monitoring a gate current because the current flows through the reverse transfer capacitance of IGBTs from the collector terminal to the gate terminal under FUL conditions. A physics-based IGBT model shows high accuracy for both static and dynamic characteristics, making it useful for developing a protection circuit for IGBTs subjected to short-circuit conditions. Simulated results using the physics-based IGBT model and experimental results verify the validity of the proposed protection circuit.

A Protection Circuit for the Power Supply of a Gas Discharge Lamp

In order to drive gas discharge lamps, DC-AC converters with a LCC resonant tank, whose output voltage is adjusted by a variable frequency control are frequently used. However, when they are activated by varying the operating frequency, converters are frequently damaged by unstable operation, due to the rising and falling of the operating frequency near the resonant frequency. To solve this problem, a simple protection circuit for the power supply of a gas discharge lamp is proposed in this paper. This circuit senses the primary current of the main transformer. Using this protection circuit, the operating frequency of the lamp driving inverter system is kept close to and on the right side of the resonant frequency and the inverter is always operated in the ZVS condition. The resulting stable variable frequency operation allows various gas discharge lamps to be tested without the risk of damaging the main switches, because the protection circuit can protect the power MOSFETs of bridge converters from abnormal conditions. The validity and effectiveness of the proposed protection circuit are verified through the experimental results.

MHD 램프용 전자식 안정기의 보호 회로 설계

본 논문에서는 전자식 안정기의 출력이 개방 또는 단락되었을 경우에 대한 보호 회로를 설계하였다. 전자식 안정기의 출력이 개방되었을 경우 일정한 주기의 고전압이 발생하여 스위치 소자에 전압 스트레스를 가하게 된다. 또한 출력이 단락되었을 경우 과전류가 흐르게 되어 안정기 발열 및 반도체 소자의 수명 감소 등 문제가 발생하게 된다. 이를 해결하고자 TTL 소자 및 수동 소자로 구성된 보호 회로를 제안하였으며 제안된 보호 회로는 저단가 구현 및 높은 신뢰성의 장점이 있다. 제안된 보호 회로를 실제 안정기에 연결하여 상황별 실험을 통하여 유용함을 증명하였다.

A New 600 V Punch Through-Insulated Gate Bipolar Transistor with the Monolithic Fault Protection Circuit Using the Floating p-Well Voltage Detection

A new fault sensing scheme of the insulated gate bipolar transistor (IGBT) employing the floating p-well, which detects the over-voltage of the floating p-well under the short circuit fault condition, is proposed and implemented by fabricating the main IGBT and gate voltage pull-down circuit using the widely used planar IGBT process. The floating p-well structure also improves the avalanche energy of IGBT in addition to detecting the fault signal. The detection of fault and gate voltage pull-down operation is achieved by the proposed fault protection scheme employing the floating p-well voltage detection. The proposed fault protection circuit was measured under the hard switching fault (HSF) and fault under load (FUL) conditions. The normal switching behavior of the main IGBT with the proposed protection circuit was also investigated under inductive load switching conditions.

Experimental study on short-circuit characteristics of the new protection circuit of insulated gate bipolar transistor

A new protection circuit employing the collector to emitter voltage (VCE) sensing scheme for short-circuit withstanding capability of the insulated gate bipolar transistor (IGBT) is proposed and verified by experimental results. Because the current path between the gate and collector can be successfully eliminated in the proposed protection circuit, the power consumption can be reduced and the gate input impedance can be increased. Previous study is limited to dc characteristics. However, experimental results show that the proposed protection circuit successfully reduces the over-current of main IGBT by 80.4% under the short-circuit condition.

A new protection circuit for high-voltage current saturation of LEST

A new protection circuit for high-voltage current saturation of a lateral emitter switched thyristor (LEST) is proposed. We fabricated this circuit by employing a widely used insulated gate bipolar transistor compatible process. A high-voltage current saturation exceeding 200 V was measured in the EST with the proposed protection circuit, while the current saturation of the conventional LEST is limited to 17 V by the breakdown of the lateral MOSFET.

A New Voltage between Collector and Emitter (VCE) Sensing Scheme for Short-Circuit Withstanding Capability of the Insulated Gate Bipolar Transistor

A new protection circuit employing a voltage between collector and emitter (VCE) sensing scheme for the short-circuit withstanding capability of insulated gate bipolar transistors (IGBTs) is proposed and verified on the basis of two-dimensional simulation and experimental results. Because the current path between the gate and the collector can be successfully eliminated in the proposed protection circuit, power consumption can be reduced and gate input impedance can be increased. The experimental results show that the proposed protection circuit can adjust the current saturation level of IGBTs and the short-circuit withstanding capability can be significantly enhanced.

A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI

A new CMOS on-chip electrostatic discharge (ESD) protection circuit which consists of dual parasitic SCR structures is proposed and investigated. Experimental results show that with a small layout area of 8800 mu /sup 2/, the protection circuit can successfully perform negative and positive ESD protection with failure thresholds greater than +or-1 and +or-10 kV in machine-mode (MM) and human-body-mode (HBM) testing, respectively. The low ESD trigger voltages in both SCRs can be readily achieved through proper circuit design and without involving device or junction breakdown. The input capacitance of the proposed protection circuit is very low and no diffusion resistor between I/O pad and internal circuits is required, so it is suitable for high-speed applications. Moreover, this ESD protection circuit is fully process compatible with CMOS technologies. >

Integrated protection circuit against the forward biasing of the input junction in digital MOS ICs

The paper presents a technique which prevents carrier injection into the substrate caused by a large negative-going signal applied to an AC-coupled input amplifier in digital MOS integrated circuits. The analysis of the phenomena and computer simulations of the proposed protection circuit are studied, showing that the injected charge is reduced to about 1 pC when the external coupling-capacitor charge C ΔV is equal to about 10 nC. Experimental data are shown for this circuit, which was used in an n-MOS infrared remote-control receiver IC.