Proposed Neuron Circuit Research Articles

An Area-Efficient Integrate-and-Fire Neuron Circuit with Enhanced Robustness against Synapse Variability in Hardware Neural Network

Neuron circuits are the fundamental building blocks in the modern neuromorphic system. Designing compact and low-power neuron circuits can significantly improve the overall area and energy efficiencies of a neuromorphic chip architecture. Here, practical neuron circuits must overcome the variations arising from nonideal behaviors of synaptic devices, such as stuck-at-fault and conductance deviation. In this study, a compact leaky integrate-and-fire neuron circuit has been designed, with resilience to synaptic device state variations, for hardware implementation of spiking neural networks (SNNs). The proposed neuron circuit is simulated on the 0.35-μm Si complementary metal-oxide-semiconductor technology node by a series of circuit simulations based on HSPICE. The proposed circuit occupies a reduced area and exhibits low power consumption (14.7 µW per spike). Furthermore, the optimized circuit design results in a high degree of tolerance toward input-current variations arising from conductance-state variations in the synapse array. Hence, the proposed neuron circuit would be capable of substantially improving the area efficiency and reliability in the realization of the hardware-oriented SNN architectures.

A Compact and Low-Power SoC Design for Spiking Neural Network Based on Current Multiplier Charge Injector Synapse.

This paper presents a compact analog system-on-chip (SoC) implementation of a spiking neural network (SNN) for low-power Internet of Things (IoT) applications. The low-power implementation of an SNN SoC requires the optimization of not only the SNN model but also the architecture and circuit designs. In this work, the SNN has been constituted from the analog neuron and synaptic circuits, which are designed to optimize both the chip area and power consumption. The proposed synapse circuit is based on a current multiplier charge injector (CMCI) circuit, which can significantly reduce power consumption and chip area compared with the previous work while allowing for design scalability for higher resolutions. The proposed neuron circuit employs an asynchronous structure, which makes it highly sensitive to input synaptic currents and enables it to achieve higher energy efficiency. To compare the performance of the proposed SoC in its area and power consumption, we implemented a digital SoC for the same SNN model in FPGA. The proposed SNN chip, when trained using the MNIST dataset, achieves a classification accuracy of 96.56%. The presented SNN chip has been implemented using a 65 nm CMOS process for fabrication. The entire chip occupies 0.96 mm2 and consumes an average power of 530 μW, which is 200 times lower than its digital counterpart.

Design and optimization of a new CMOS high-speed H–H neuron

Balance among inter-spike interval (ISI), power consumption and biological reality is one of the major concerns of the Hodgkin-Huxley neuron circuit design trade-off. This paper proposed a CMOS high-speed H–H neuron circuit design. The three current channels in the theoretical H–H model were achieved by 180-nm CMOS circuits. For accurate measurement, input and output modules are integrated with the proposed neuron circuit. For validation of circuit design, the proposed neuron circuit is fabricated by the 180-nm 1P6M CMOS process. The active area of the fabricated H–H neuron circuit is about 0.018 mm2. With 1.8 V input, power consumption of the proposed H–H neuron is around 111.3 μW. Test results have a good agreement with simulation results. For optimization of the proposed neuron circuit, relationship between the on-chip capacitance and the ISI was analyzed via a simulation based orthogonal Design of Experiment (DoE). It has found that the ISI of the proposed neuron circuit decreases exponentially with value of two on-chip capacitor. Among two critical capacitors, the repolarization capacitor has a greater influence on the ISI than the membrane capacitor.

RRAM-Based Energy Efficient Scalable Integrate and Fire Neuron With Built-In Reset Circuit

In this brief, we propose a Resistive Random Access Memory (RRAM) based self-resetting Integrate and Fire ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}\&amp;\text{F}$ </tex-math></inline-formula> ) neuron. The proposed neuron circuit does not require any external bias voltage and the integration of control unit required to reset RRAM into neuron circuit optimizes its overall power consumption. The neuron circuit proposed in this brief consists of two RRAMs for integrate and fire operations, whereas, pulse propogation and reset circuit consists of 22 CMOS transistors. It consumes <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.5~fJ$ </tex-math></inline-formula> per spike, which is 48% and 53% less than the recent neurons designed using, nanoscale FBFET and PDSOI-MOSFET, respectively. The operating frequency of proposed neuron ranges from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$277~KHz$ </tex-math></inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$03~MHz$ </tex-math></inline-formula> , which is at least 7.5% and 10% higher than the operating frequencies of above mentioned recent neurons, respectively. The inclusion of reset circuit into RRAM based neuron circuit enables the implementation of large scale spiking neural network (SNN), which makes it superior in terms of power and energy consumption.

FinFET-based non-linear analog signal processing modules

FinFETs exhibit far superior transistor characteristics (better gate control and a lower sub-threshold slope) as compared to the standard MOSFETs, this paper first employs the FinFETs in the design of an operational transconductance amplifier (OTA). The FinFET-based OTA offers a linearity range and - 3 dB bandwidth of ± 300 mV and 631.81 GHz, respectively. Further, the non-linear applications of the proposed OTA, viz. voltage divider, memristor emulator, and a memristive neuron, are presented. The proposed analog voltage divider circuit contains one OTA and two external N-FinFETs. The maximum bandwidth obtained for the voltage divider is 217.54 GHz. The memristor emulator contains one OTA, two external N-FinFETs, and one grounded capacitor. The proposed emulator circuit follows the signature characteristics of the actual memristor device. The frequency response characteristics of the proposed emulator circuit depict a bandwidth of 22.7 GHz. The proposed emulator shows non-volatile as well as electronically tunable features. Next, Monte-Carlo simulation analysis has been performed on the proposed circuits in order to observe the effects of statistical variation in different operating conditions. Furthermore, we propose a FinFET-based passive memristive neuron model using a memristor emulator circuit. The proposed neuron circuit follows a tangent hyperbolic activation function. All the proposed circuits are suitable for monolithic implementation. The proposed circuits are verified using 20 nm FinFET technology. The simulation results obtained using HSPICE agree well with the theoretical analysis.

An integrate-and-fire neuron with capacitive trans-impedance amplifier for improving linearity in Spiking Neural Networks

In this paper, we propose a novel neuron circuit with capacitive trans-impedance amplifier (CTIA) integrator to enhance the linearity of pre-synaptic current summation. The proposed neuron circuit achieved an improvement compared to the conventional neuron circuit with a current mirror, thereby maintaining the input node of a neuron circuit at virtual ground by the negative feedback of an amplifier. The relative potential difference is integrated into the membrane capacitor of CTIA feedback loop with a negative integration. From the simulation results, we confirmed that the proposed neuron circuit successfully improves output linearity for a wide range of the input current level.

Spiking and chaotic behaviours of locally active memristor‐based neuron circuit

This brief designs an artificial neuron circuit consisting of an inductor and an N-type locally active memristor (LAM). When the presented neuron circuit is excited by the DC or sine voltage signal, it can pick up the most significant features of a biological neuron: all-or-none, spiking oscillation, and chaotic behaviours. Local activity and edge of chaos theories are applied to analyze the electrical characteristics of the neuron circuit. Furthermore, the spiking mechanism of the circuit exhibits is investigated. The circuit implementation of the proposed neuron circuit is presented. Both simulation and experimental results demonstrate the practicability of the proposed neuron circuit and the validity of the theoretical analysis.

Silicon Modeling of Spiking Neurons With Diverse Dynamic Behaviors

Since spiking neural networks (SNNs) can effectively simulate the information processing mechanism of the biological cortex, they are expected to bridge the gap between neuroscience and machine learning. The hardware simulation of large-scale SNNs requires a simple and versatile silicon neuron model framework. In this article, a spiking neuron circuit as the core device of SNNs is presented. The proposed neuron circuit can mimic the dynamics of different types of biological neurons by adjusting the bias voltage. In order to facilitate the implementation of the spiking neuron circuit based on complementary metal-oxide-semiconductor (CMOS) and reduce the overhead of the circuit area, a modified Mihalas–Niebur (MN) mathematical model is adopted. The improved MN model is biologically plausible and can still successfully display all dynamic behaviors observed in biology. The function of the proposed neuron circuit has been verified by the phase diagram analysis method. The simulation results show the designed neuron circuit can successfully replicate 15 of the 20 firing patterns exhibited by the biological cortex, which proves that the neuron can act as a universal spiking neuron in very large-scale integrated circuit (VLSI) neuromorphic networks.

FPGA implementation of piecewise linear spiking neuron and simulation of cortical neurons

Modeling and hardware implementation of artificial neurons is an important goal in the field of neuromorphic and brain-inspired computing. This paper presents a hardware implementation method of the two-dimensional piecewise linear spiking neuron (PLSN) model that can express various dynamical behaviors under different bifurcation mechanisms. The neuronal digital circuit of the PLSN model is designed and implemented on a field programmable gate array (FPGA), where all computation processes in the arithmetic tree are pipelined to maintain fast computing. The hardware is used to demonstrate 20 neurocomputational properties that are the most prominent dynamical behaviors of biological neurons. The 6 cortical neurons are also simulated using the PLSN circuit on FPGA. The results show that the proposed neuron circuit can express complex spiking and bursting behaviors of cortical neurons.

An ultra-compact leaky integrate-and-fire neuron with long and tunable time constant utilizing pseudo resistors for spiking neural networks

Spiking neural networks (SNNs) inspired by biological neurons enable a more realistic mimicry of the human brain. To realize SNNs similar to large-scale biological networks, neuron circuits with high area efficiency are essential. In this paper, we propose a compact leaky integrate-and-fire (LIF) neuron circuit with a long and tunable time constant, which consists of a capacitor and two pseudo resistors (PRs). The prototype chip was fabricated with TSMC 65 nm CMOS technology, and it occupies a die area of 1392 μm2. The fabricated LIF neuron has a power consumption of 6 μW and a leak time constant of up to 1.2 ms (the resistance of PR is up to 600 MΩ). In addition, the time constants are tunable by changing the bias voltage of PRs. Overall, this proposed neuron circuit facilitates the very-large-scale integration of adaptive SNNs, which is crucial for the implementation of bio-scale brain-inspired computing.

A π-Type Memristor Synapse and Neuron With Structural Plasticity

A synaptic structure with memristor state initialization function and a neuronal circuit with structural variability are presented in this article. In contrast to the popular use of voltage as a medium for containing information and realizing the computational function of a neuron in the form of voltage–current–voltage, the proposed neuron circuit adopts current as a carrier of information; also the computation will be realized in the form of current–voltage instead. Since the sum of currents can be achieved by direct connection, this will greatly reduce the hardware area of the artificial neuron. In addition, by adjusting the switches, the initialization of the memristor can be implemented, and the process of structural changes of neurons in biology can also be mimicked. Comparing with several popular synaptic circuits, it is proven that the π-type synapse has more structural advantages. Simulations show that the π-type synaptic structure can obtain the specified weight value faster and complete the initial state setting of the memristors in 1.502 ms. Even in the worst case, where the weight needs to be changed from −1 to 1, it can be completed in only 1.272 ms. Under the condition of achieving the same function, the area of the proposed neuron with 100 synapses will be reduced by at least 97.42%. Moreover, there is better performance in terms of linearity.

Neuromorphic behaviors of N-type locally-active memristor

Owing to the advantages of high integration, low power consumption and locally active characteristics, locally-active memristor (LAM) has shown great potential applications in neuromorphic computing. To further investigate the neuromorphic dynamics of LAMs, a simple N-type LAM mathematical model is proposed in this work. By analyzing its voltage-current characteristic and small-signal equivalent circuit, a neuron circuit based on the N-type LAM is designed, where a variety of neuromorphic behaviors are successfully simulated, such as “all-or-nothing” behavior, spikes, bursting, periodic oscillation, etc. Moreover, Hopf bifurcation theory and numerical analysis method are used to study the dynamics of the circuit quantitatively. Then, an artificial tactile neuron and its frequency characteristics are presented by using the proposed neuron circuit topology. The simulation results show that when the amplitude of the input signal is lower than the threshold, the oscillation frequency of the output signal of the artificial neuron circuit is positively correlated with the intensity of the input signal, and reaches a maximum value at the threshold. The above frequency characteristics are consistent with those of the exciting state of biological sensory system. Subsequently, if the incentive intensity continues to increase, the oscillation frequency will gradually decrease, corresponding to the protective inhibition behavior. Finally, the physical circuit of the N-type LAM, and artificialneuron circuit are realized. The experimental results accord well with the simulation results and theoreticalanalyses, manifesting the practicability of the N-type LAM model and the feasibility of artificial neuron circuit.

Improving TID Radiation Robustness of a CMOS OxRAM-Based Neuron Circuit by Using Enclosed Layout Transistors

Aerospace applications are attractive candidates to embed artificial neural networks despite their excellent parallel processing capability and reduced energy consumption. Nonetheless, the long-term exposure to incidence levels of ionizing radiation may degrade their physical components reducing, therefore, their reliability and expected lifetime. Thus, it is mandatory to face the challenge of enhancing the radiation hardening characteristics of a neural circuit before operating in harsh environments. A possible solution to substantially reduce long-term spurious effects caused by ionizing radiation [referred to as total ionizing dose (TID)] is to change the conventional rectangular MOS gate geometry to a nonstandard topology referred to as an enclosed layout transistor (ELT). In the context of hardening a complete neuron circuit against TID effects, together with the well-established ELT paradigm, it is possible to exploit the inclusion of other hardened devices, for instance, the memory element. In this sense, the Oxide-based Resistive Random Access Memory (OxRAM) can be used as the memory element, which is inherently tolerant against ionizing radiation and, hence, better suited for a fully hardened circuit. In this work, we propose to harden the design of an existing OxRAM-based neuron circuit through the inclusion of ELTs, i.e., to improve the radiation hardening characteristics of a preexistent convenient neuron circuit topology by using the enclosed gate geometry for the nMOS and pMOS devices. Electrical simulations, considering a standard commercial bulk CMOS fabrication process, in a 180-nm technology, have been carried out to validate our proposed design. In addition, we exploit two simulation setups: first, the OxRAM's behavior in a simple circuit configuration, to provide a better understanding of the OxRAM device; second, the OxRAM-based neuron circuit, to evaluate the behavior of the proposed neuron circuit hardened with ELTs. The simulation results, supported by the analysis of former works regarding the incidence of ionizing radiation in OxRAM and ELTs, indicate that the proposed hardened neuron circuit is a feasible solution to embed neuromorphic computing in aerospace applications.

A Novel Memristive Chaotic Neuron Circuit and Its Application in Chaotic Neural Networks for Associative Memory

In this article, we propose a novel chaotic neuron circuit with memristive neural synapses, construct an architecture of memristive chaotic neural network (MCNN) and implement associative memory application of bipolar images. The proposed neuron circuit mainly consists of synapse module and neuron module with chaotic dynamics characteristics. The synapse module is composed of memristors which represent synaptic weights. The neuron module employs voltage feedback operational amplifiers to accomplish integral operation and output function. MCNN utilizes a memristor crossbar array to perform matrix operations and can process the information in parallel. In addition, the proposed circuit of MCNN can accomplish continuous recursive operations and meet different applications due to the programmability of the memristor. The ex-situ method is utilized to train the memristor crossbar array. Furthermore, the associative memory applications of bipolar images are carried out based on the constructed circuits of MCNN with three and nine neurons. The simulation results in PSPICE software testify the functions of the MCNN circuit.

Low-Power Binary Neuron Circuit With Adjustable Threshold for Binary Neural Networks Using NAND Flash Memory

Recent studies have demonstrated that binary neural networks (BNN) could achieve a satisfying inference accuracy on representative image datasets. BNN conducts XNOR and bit-counting operations instead of high-precision vector-matrix multiplication (VMM), significantly reducing the memory storage. In this work, an analog bit-counting scheme is proposed to decrease the burden of neuron circuits with a synaptic architecture utilizing NAND flash memory. A novel binary neuron circuit with a double-gate positive feedback (PF) device is demonstrated to replace the sense amplifier, adder, and comparator, thereby reducing the burden of the complementary metal-oxide semiconductor (CMOS) circuits and power consumption. By using the double-gate PF device, the threshold voltage of the neuron circuits can be adaptively matched to the threshold value in the algorithms eliminating the accuracy degradation introduced by the process variation. Thanks to the super-steep SS characteristics of the PF device, the proposed neuron circuit with the PF device has an off-state current of 1 pA, representing 10 5 times improvement compared to the neuron circuit with a conventional metal-oxide-semiconductor field effect transistor (MOSFET) device. A system simulation of a hardware-based BNN shows that the low-variance conductance distribution (8.4 %) of the synaptic device and the adjustable threshold of the neuron circuit implement a highly efficient BNN with a high inference accuracy.

Implementation of homeostasis functionality in neuron circuit using double-gate device for spiking neural network

The homeostatic neuron circuit using a double-gate MOSFET is proposed to imitate a homeostasis functionality of a biological neuron in spiking neural networks (SNN) based on a spike-timing dependent plasticity (STDP). The threshold voltage (Vth) of the double-gate MOSFET is controlled by independent two-gate biases (VG1 and VG2). By using Vth change of the double-gate MOSFET in the neuron circuits, the fire rate of the output neuron is controlled. The homeostasis functionality is implemented by the operation of multi-neuron system based on the proposed neuron circuit. Through the SNN based on STDP using MNIST datasets, it is demonstrated that the recognition rate (~91%) of the SNN with the proposed homeostasis functionality is higher than that (~79%) of the SNN without the proposed homeostasis functionality. Also, the results of the recognition rate with the variations (σ/μ < 0.5) of the synaptic devices and the initial Vth of neuron circuits show a low degradation (1 ~ 3%) in the recognition rate. Thus, it is demonstrated that the homeostasis functionality of the proposed neuron circuit has the immunity to variations (σ/μ < 0.5) of the synaptic devices and the neuron circuits in the SNN based on STDP.

Memristor-Based Circuit Implementations of Recognition Network and Recall Network With Forgetting Stages

This paper proposes a novel memistor-based neuron circuit, in which the memristor-CMOS hybrid synaptic circuit simply utilizes the positive voltage to change the memristance. At the same time, in order to obtain the memristance and output voltage changes in the neuron circuit, a mathematical deduction is implemented according to the circuit structure. Then, the memristor-based recognition and recall network circuits are constructed based on the proposed neuron circuit. The recognition and recall functions are realized by associative learning between the unconditional stimuli and the conditional stimuli (CS). After the learning stages, the single presentation of CS activates forgetting stages in the two networks. Furthermore, the related parameter changes in the learning and forgetting stages can be calculated by the deduced equations approximately. The PSPICE simulations are implemented to demonstrate the effectiveness of the proposed circuits and the deduced equations.

Integrate-and-fire neuron circuit using positive feedback field effect transistor for low power operation

In this work, we fabricated a dual gate positive feedback field-effect transistor (FBFET) integrated with CMOS. We investigated the DC and transient characteristics of the FBFET. The fabricated FBFET has an extremely low sub-threshold slope of less than 2.3 mV/dec and low off-current. We also propose an analog integrated-and-fire neuron circuit incorporating a FBFET, which significantly reduces the power dissipation of hardware neural networks. In a conventional neuron circuit using a membrane capacitor to integrate input pulses, most of the energy is consumed by the first inverter stage connected to the capacitor. Since the membrane capacitor is charged slowly compared to digital logic, a large amount of short-circuit current flows between Vdd and ground in the first inverter during this period. In the proposed neuron circuit, the short-circuit current is significantly suppressed by adopting a FBFET in the inverter. Through TCAD mixed mode simulation of the device and the circuit, we compare the energy consumption of a conventional and the proposed neuron circuits. In a single neuron circuit with microsecond duration pulses, 58% of the energy consumption is reduced by incorporating a FBFET. We performed SPICE compact modeling of FBFET, and its parameters were fitted to match the measurement results of the fabricated FBFET. Then, we conducted a circuit simulation to verify the operating neural networks. We implemented a single layer spiking neural network (SNN) that had resistive synaptic devices. In the SNN simulation, approximately 94% of the average power consumption of all output neurons was reduced.

Voltage regulation of retina neuron model with dynamic feedback for biological acquisition image

The investigation on biological activated imagers using standard CMOS processes has become continuous trend where silicon retina with central-plane image processing, small pixel sizes, large dynamic range and relatively low power consumption are required. This work proposes a voltage regulation of retina neuron model with dynamic feedback approach for biological acquisition image. The implementation of retina neuron circuit consists of conventional current-feedback event generator with the extension of proposed current mirror and dynamic feedback stage. The proposed neuron circuit achieves extremely high dynamic voltage range with respect to light intensity which help to detect biological acquisition image and could be beneficial for retinal prostheses. Moreover, individually modelling of photodiode using Verilog-A and device model is proposed for activation of current-feedback event generator. This modeling of photodiode permits to simple, compact and linear solution for pixel implementation. The proposed voltage controlled retina neuron circuit is implemented and fabricated using 0.18 μm Magnachip CMOS process. The spikes of output voltage are varied according to the inputs taken as control voltage and light intensity. As per the observation, read-out spikes of output voltage pulses provide more brightness level in the image pixels. The fabrication of proposed neuron circuit achieves less power consumption in nano-joule under dc supply of 3.3 V. The experimental result of output voltage is made good correlation with simulated one.

Design of a new CMOS Low-Power Analogue Neuron

In this paper, a low-power analogue complementary metal oxide semiconductor (CMOS) artificial neuron circuit is presented. The analogue neuron is composed of multiplier and programmable activation function circuits. The proposed four-quadrant multiplier has a single ended current output which eliminates the extra summation circuit at the output of the neuron that reduces the chip area as well as power consumption. In addition, programmability of activation function improves the neural network design process while enables the proposed neuron circuit to be used properly in learning algorithms such as back propagation. The most important feature of the proposed circuit is low power consumption and simple circuit topology. The performance of the circuit is confirmed by HSPICE simulations using 0.18 μm CMOS technology parameters. The circuit operates at 1 V supply voltage and consumes only 15 μW. Finally, different neural networks are realized using the proposed neuron circuit, which are successfully used to solve exclusive OR (XOR) problem and region classification problem to verify the accuracy and performance of the proposed circuit.