Proposed Multilevel Inverter Topology Research Articles

Low-cost single-source 17 level multilevel inverter with reduced switch count

Abstract This paper introduces an innovative multi-level inverter (MLI) topology operating with a single DC source. The proposed structure consists of a DC-DC rectifier (HFL), a switched capacitor (SC) unit and a Packaged U-Cell (PUC) module. The topology synthesizes 17 voltage levels at the output with only 10 power switches, offering low control complexity and high power efficiency. The high number of levels at the output voltage provides a high quality output voltage wave. A soft charging cell (SCC) is used to suppress impulsive charging currents in the switched capacitors. Experimental results show that SCC effectively suppresses impulsive currents in switched capacitors. The high frequency link (HFL) used to provide high voltage gain improves the cost efficiency of the system by reducing transformer sizes and costs. Simulation and experimental results show that the proposed topology achieves 96.92% efficiency, near sinusoidal current output and total harmonic distortion (THD) values between 4.99% and 1.23%. Moreover, with a low cost function (CF) value of 1.60, it is proven to offer a viable alternative for applications such as Renewable Energy Systems (RES) and Electric Vehicles (EVs). These findings demonstrate the applicability of the proposed MLI topology in these areas with low cost, high efficiency and quality power output.

Modelling and Simulation of Crisscross Switched Multilevel Inverter Using Cascaded Semi-Half-Bridge Cells

A new cascaded multilevel inverter (MLI) is presented. This MLI aims to use a lesser number of switches, achieve better modularity, and reduce voltage stress. The new structure can operate in symmetric and asymmetric modes, producing all odd and even voltage levels. It comprises semi-half-bridge cells connected in series with crisscross switches to generate target voltage levels for synthesizing the sinusoidal output waveform. An extended version of the proposed MLI topology cascades sub-inverters to generate more voltage levels with reduced standing voltage. Compared to the cascading H-bridge topology, the proposed MLI and its extended version use fewer semiconductor switches. The MATLAB R2013b-based simulation results, confirm the efficacy of the proposed MLI topology.

Performance evaluation of a 15-level inverter using two DC sources with lower standing voltage

ABSTRACT Most of the reduced switch multilevel inverters (MLIs), including switched capacitor MLIs (SC-MLIs), are designed with voltage sources/capacitors have obtained voltage levels with the addition of these sources only. This increases the number of voltage sources (capacitors) without full utilisation of these sources and has higher inverter total standing voltages, which leads the inverter inefficient (high conduction loss) and costly. The motivation of this work is to design a generalised reduced component MLI aiming for addition as well as subtraction of the voltage sources to obtain a voltage level, which results in the reduction of sources, enhance the voltage utilisation and lowering the inverter total standing voltage (TSV). The design parameters of the proposed MLI topology are compared with the recently developed MLIs in terms of the number of switches, capacitors and TSV to prove its superiority. The experimental prototype of the specimen 15-level and 27-level inverters is implemented using DS1103 and the corresponding results are presented.

Transformer Based 25-Level T-Type MLI for Renewable Energy Integration

The primary challenge with cascaded H-bridge multilevel inverters (MLI) is the need of a large number of switching components and distinct dc-sources for integration of renewable energy to medium voltage grid. As a result, in these types of systems, component minimization is crucial. With the advent of transformer cascaded multilevel inverters (TCMIs), multiple dc sources in cascaded H-Bridge (CHBs) are no longer required for operation. According to the findings of this research, a novel transformer cascaded MLI with 25 levels and 12 switches can be implemented using a single dc source. The proposed MLI is comprised of two different rated isolated transformers. The proposed MLI topology offers the structural advantage of fewer semiconductor components, provides self-galvanic isolation, and generates uniform voltage levels for all turn's ratio. Furthermore, the MLI employs a switching mechanism known as nearest level control, which reduces device power loss and, hence, enhances the systems overall efficiency. To assess the performance of the proposed TCMLI, a laboratory prototype was built and simulations in the MATLAB/Simulink environment were run. In addition, a study of the systems power loss analysis has been presented. A comparison of the proposed topology to other recent topologies of a similar nature is also provided.

Floating-capacitor based inverter for open-ended winding induction motor drive with fault-tolerance

ABSTRACT Floating-capacitor-based nine-level inverter topology for open-ended winding induction motor (OWIM) drive is presented in this paper. The proposed multilevel inverter topology (PMLIT) essentially consists of four three-phase two-level voltage source inverters (VSI), three isolated DC sources and a floating-capacitor (FC). Out of four inverters, three inverters are fed from DC sources, and the fourth inverter is connected with the FC. The advantage of the PMLIT is that the maximum output voltage will be twice the source voltage with nine levels across each phase winding. The PMLIT employs least number of components which makes the inverter cost-effective and has lowered control complexity. The PMLIT can deliver seven, five or three-level output voltage with a decrease in modulation index. Conventional sinusoidal pulse-width modulation (PWM) techniques can be employed to generate switch-gate pulses. The intermediate-voltage levels are realised by proper charging and discharging of the FC. The performance of the PMLIT under possible switch faults is investigated, and modified switching logics are proposed to deliver a balanced supply for the OWIM drive in post-fault operation. Simulations are performed in the MATLAB/Simulink environment, and an experimental setup is designed to validate the simulations, and the results are presented.

A Generalized High Gain Multilevel Inverter for Small Scale Solar Photovoltaic Applications

The contribution of renewable energy, especially small-scale solar photovoltaics (PV), is increasing exponentially in the energy sector. In general, high gain DC-DC converters are used as front-end converters to increase the low voltage of PV panels; further, the DC-AC converter (multilevel inverters) is used for standalone AC loads or grid integration. To avoid the front-end converter and achieve both objectives, this paper proposes a nine-level quadruple boost inverter topology for small-scale solar PV applications. The proposed topology operates on a switched capacitor technique to boost the voltage, and has self-voltage balancing of capacitors. This paper presents the detailed operation of the proposed nine-level inverter, voltage stress calculations, loss analysis, and designing of circuit parameters. In addition, a high-gain generalized multilevel inverter (MLI) topology is also reported. Furthermore, the proposed MLI is compared with competitive inverters available in the recent literature. The proposed MLI topology has advantages such as a minimum total standing voltage and a reduced component count; it can also produce bipolar voltage inherently. The performance of the proposed MLI topology is validated through the MATLAB-based simulations and an experimental prototype. Further, the experimental results are presented by considering load variations, modulation index variations, and output frequency variations. The experimental efficiency obtained is in the range of 96.2% to 92.8% for proposed 9-level inverter.

A multi‐string fault‐tolerant multilevel inverter configuration for off‐grid photovoltaic applications

With the intensified demand for enhanced harmonic profile of output voltage, better power quality, reduced dv/dt stress of devices and minimal filter requirement, multilevel inverters (MLIs) have emerged as a viable solution in renewable energy applications. In the conventional MLI, the order of device count, as well as control complexity, will increase with respect to the number of voltage levels. Moreover, this higher order of semiconductor devices may increase the chance of failure rate, which degrades the reliability of the inverter. To address these issues, in this article a 1-Φ fault-tolerant MLI topology is proposed for multi-string photovoltaic (PV) applications with reduced device count as well as improved reliability. This topology required four isolated DC sources with a voltage magnitude of Vdc/4 (where Vdc is the voltage requirement for the conventional neutral point clamped MLI), which are realized with multiple PV strings. The proposed MLI enhances the reliability of the system in terms of switch open circuit failures as well as source failures. Moreover, as compared to other conventional MLIs, the proposed MLI topology has the energy balancing capability between sources during partial shading condition of PV panels. The mathematical analysis of energy balancing between the DC sources is also presented in this article. The proposed 1-Φ MLI has been analyzed for various source failures and/or switch open circuit failures using MATLAB/Simulink as well as by implementing the laboratory prototype.

Mathematical analysis of cost function and reliability condition for new proposed multilevel inverter topology

<span>In this paper cost function and reliability analysis of classic novel symmetric multilevel inverter topology has been presented. Cost function and reliability analysis are the economical factors of the effieciency of an inverter, this made the intrest in this area.cost function deneotes the cost of the inverter based on the power flow, reliability explain the mean time failure propotional to the life span. Firstly the cost function of the novel topology has been proposed using mathematical calculation using various current rating and the results are validated compared with exiting topology. Secondly reliability approach is used to evaluate the reliability of the switch with respect to the failure rate and mean time period of the switch using fedis and markow reliability analysis equations and the results are evaluated for all the switches present in the topology. And the results are the compared with the conventional multilevel inverter, cost function and reliability analysis of the proposed multilevel inverter.</span>

A generalized symmetrical MLI topology with improved commutation

A generalized symmetrical multilevel inverter (MLI) topology with an essential feature of smooth commutation during the dead time for inductive loads is presented in this paper. It consists of a level generation unit (LGU) and polarity generation unit (PGU); Both LGU and PGU provide a freewheeling path for load current during the dead time for an inductive load which avoids large voltage spikes across the output. This topology can also generate the required number of levels at the output with a minimum number of components. As it requires fewer components, switching losses, installations space, and cost of the implementation are low. In this paper, a seven-level structure derived from the generalized topology is considered for detailed analysis. Further, to show the effectiveness of the proposed MLI topology over the existing symmetrical topologies in overcoming commutation problem, simulations were performed and are validated with experimental results. A comparative study is made in terms of power switches, power diodes, clamping capacitors, and driver circuits between traditional, recent, and proposed topologies.

A Novel Higher Level Symmetrical and Asymmetrical Multilevel Inverter for Solar Energy Environment

ABSTRACT In this paper, a higher level symmetrical and asymmetrical multilevel inverter (MLI) with reduced device count is proposed for renewable energy systems. Multilevel inverters are recently gaining importance in renewable energy systems and other DC to AC conversion applications due to reducing voltage stress, low total harmonic distortion (THD) and high-quality output as compared to classical inverters. This paper present a basic cell unit of reduced device count (RDC) MLI with six switching devices is proposed. The topology has advantages of reduced device count over existing topologies for the same number of output levels, thus improving operating efficiency and reliability. Upon cascading two such basic cells with 12 devices synthesizes a 49 level output with an estimated THD of 1.63%. The other advantages accrued due to reduced device count are a reduction in switch driver circuits, less number of required dc voltage sources, less installation space and reduction in cost. The major benefit of the proposed topology is that it can deliver power from an asymmetrical source to load even under sudden variation in environmental conditions. The proposed MLI topology is simulated in MATLAB/Simulink environment and a laboratory prototype is developed and tested in the lab. The control paradigm is developed as the Simulink model, which is interfaced with dSPACE DS-1104 for generating control pulses to drive switches of proposed MLI topology. The experimental results validate the concept and paradigm of the proposed MLI topology.

A Fault-Tolerant Multilevel Inverter Topology With Preserved Output Power and Voltage Levels Under Pre- and Postfault Operation

Low reliability is one of the significant worries of a multilevel inverter (MLI) and which results due to the presence of a higher number of switches and capacitors as compared with the conventional two-level inverter. Consequently, the fault-tolerant (FT) operation of MLI has attracted significant research attention. Therefore, in this article, a nine-level inverter topology with FT characteristics is discussed. The proposed topology is capable of tolerating short-circuit and open-circuit faults not only in the single switch but also in multiple switches. It preserves output power, voltage levels, and capacitor voltage balancing under pre- and postfault operation. The proposed MLI topology requires the least number of dc sources, capacitors, switches, clamping diodes, and total blocking voltage in comparison to recently proposed topologies. Thus, offering better efficiency profile under pre- and postfault conditions. The proposed work has been validated experimentally with a laboratory prototype.

Fault tolerant architecture of an efficient five‐level multilevel inverter with overload capability characteristics

Multilevel inverters (MLIs) are gaining the widespread attention in various industrial applications. However, the advantages offered by MLIs are only met with the employment of a high number of semiconductor switches and capacitors, which are most vulnerable amongst all the power electronic components. Thus, designing of a reliable MLI topology is a need of the present hour. In this regard, a five-level fault tolerant MLI topology has been proposed here. The proposed MLI topology comprises the main inverter topology and a redundant leg. The main inverter topology comprises bidirectional switches which result in high power losses under both healthy and faulty conditions. Eighteen different cases arising from the inherent redundancy available in the main inverter topology have been analysed to achieve the optimum solution for obtaining high efficiency. A novel redundant leg architecture has been designed, which achieves significantly improved efficiency under all faulty conditions. Under overload conditions, the proposed redundant leg architecture is capable of reducing the current stress on the main inverter switches. An effective qualitative and quantitative comparison of the proposed topology with the recent literature has been presented. The feasibility of the proposed concepts has been verified by the obtained simulation and hardware results.

A Symmetrical Multilevel Inverter Topology with Minimal Switch Count and Total Harmonic Distortion

A multilevel inverter (MLI) with reduced number of power devices, especially for the higher output levels, is presented in this paper. The generalized topology for ([Formula: see text]) level MLI is developed with symmetrical isolated dc sources and ([Formula: see text]) number of switches. A five-level MLI is developed with five power switches and then by adding each one additional switch two more levels are added in the output voltage waveform. With the help of lookup table, the working principle of the proposed five-level MLI topology is explained. Sinusoidal pulse width modulation–phase disposition control technique has been used to get a minimal total harmonic distortion (THD). The proposed MLI topology is simulated on the MATLAB platform. The laboratory prototype is developed for five-level MLI, and the experimental results obtained validate the simulation studies. The dSPACE 1104 is used for generating gate pulses in case of experimentation. The output voltage and current THDs obtained are 9.20% and 4.60%, respectively; the harmonics are mitigated more with five-level inverter. The proposed topology is compared with the cascaded H-bridge multilevel inverter.

Implementation of Hybrid GSA SHE Technique in Hybrid Nine-Level Inverter Topology

The recent trend in multilevel inverters (MLIs) is to produce the high quality staircase ac voltage waveform while utilizing the optimum number of switching devices. In this context, this article presents a combination of topological and modulation scheme-based solution for the optimum performance of MLI. A concept of adaptable dc voltage link in conjunction with modified H-bridge unit is introduced to reduce the number of switching devices. Further to improve the quality of voltage waveform and to reduce the switching losses in the proposed topology, a hybrid gravitational search algorithm (GSA) selective harmonic elimination (SHE) technique is proposed and implemented on the newly developed MLI topology with symmetric dc sources. Comparative analysis is performed with the conventional and existing hybrid cascaded MLI topologies, which exhibits the superiority of the proposed topology in terms of reduction in count of switching devices, count of components, and conduction losses. The efficacy of the proposed hybrid GSA SHE technique is shown in the simulated results. The feasibility of the proposed MLI topology and SHE technique is further verified by the experimental results of a nine-level inverter with both equal and unequal dc sources.

A Home-type (H-type) Cascaded Multilevel Inverter with Reduced Device Count: Analysis and Implementation

Multilevel inverter (MLI) is increasingly recognized as a low distorted wave synthesizing power converter built using recent power semiconductor devices. However, MLIs suffer from the requirement of higher device count. In this paper, a 15-level Home-type (H-type) inverter topology is proposed to address this concern. The H-type inverter topology is cascaded to synthesize a higher number of levels in output voltage. Voltage ratings of the dc sources are designed to generate a large number of uniform steps in output voltage. Analysis of the proposed method is presented for required number of switches, dc voltage sources, driver circuits and blocking voltage of switches. Comparative study demonstrates that the suggested topology requires reduced device count compared to the similar topologies reported in the literature. Simulation and experimental studies have been carried out to validate the performance of proposed MLI topology.

Modified H‐bridge inverter based fault‐tolerant multilevel topologyfor open‐end winding induction motor drive

This study presents a three-phase modified H-bridge based multilevel inverter(MLI) topology for an open-end winding induction motor drive (OEWIMD). Theoperation of the proposed topology under open-circuit and short-circuit faultconditions of a switch is investigated. Proposed MLI topology is designed withthree three-phase modified H-Bridge inverters connected in a star configurationto feed an OEWIMD. This topology has advantage of delivering a maximum voltageof twice the supply voltage and is replicated as nine levels in the phasewindings of OEWIMD, thereby reducing the total harmonic distortion. Therefore,lower voltage rating sources such as solar cells or fuel cells can be used forthis topology. This topology becomes cost effective since the operating voltagerange required for the devices is less. Controlling methods such as conventionallevel-shifted and multi-reference sinusoidal pulse width modulation techniquescan be applied for this topology. A fault-tolerance strategy is proposed forinverter switch open-circuit and short-circuit faults that adds fault-tolerancecapability to the proposed topology. Simulations were performed usingMATLAB/Simulink and experimental results are presented for both normal operatingand fault-tolerance mode that confirms the inherent fault-tolerance property ofthe proposed MLI topology.

GA Based Selective Harmonic Elimination for Multilevel Inverter with Reduced Number of Switches: An Experimental Study

In power electronic applications, especially high power and medium voltage, multilevel inverters (MLIs) have been commonly used. MLIs ensure high quality load voltage and lower Total Harmonic Distortion (THD) than traditional inverter. In this paper, a multilevel inverter structure with reduced number of power switches is proposed. The proposed multilevel inverter is lower costed than conventional MLI. Also, a Genetic Algorithm (GA) based Selective Harmonic Elimination (SHE) technique has been used for the first time in the proposed MLI structure with reduced number of switches. The proposed GA based SHE technique computes the optimum switching angles by solving nonlinear harmonic equations of multilevel inverter. Both Isochronous switching (IS) and SHE techniques have been applied to proposed MLI to demonstrate the effectiveness of the GA based SHE technique. Simulation and experimental results for 7, 11 and 13-level have been obtained. Results of 11-level inverter is analysed and given in detail. Results have clearly proved that desired order harmonics in proposed MLI topology can be eliminated by using GA based SHE technique and lower THD on the load voltage has been provided.

Simulation and Analysis of Novel Extendable Multilevel Inverter Topology

Multilevel inverter (MLI) has become more popular in high power, high voltage industries owing to its high quality output voltage waveform. This paper proposes a novel single phase extendable type MLI topology. The term ‘extendable’ is included since the presented topology can be extended with maximum number of dc voltage sources to synthesize larger output levels. This topology can be operated in both symmetrical and asymmetrical conditions. The major advantages of the proposed inverter topology include minimum switching components, reduced gate driver circuits, less harmonic distortion and reduced switching losses. The comparative analysis based on the number of switches, dc voltage sources and conduction switches between the proposed topology and other existing topologies is presented in this paper. The comparison results show that the proposed inverter topology requires fewer components. The performance of the proposed MLI topology has been analyzed in both symmetrical and asymmetrical conditions. The simulation model is developed using MATLAB/SIMULINK software to verify the performance of the proposed inverter topology and also the feasibility of the presented topology during the symmetrical condition has been validated experimentally.

Optimal Design of a New Cascaded Multilevel Inverter Topology With Reduced Switch Count

Multilevel inverters (MLIs) are a great development for industrial and renewable energy applications due to their dominance over conventional two-level inverter with respect to size, rating of switches, filter requirement, and efficiency. A new single-phase cascaded MLI topology is suggested in this paper. The proposed MLI topology is designed with the aim of reducing the number of switches and the number of dc voltage sources with modularity while having a higher number of levels at the output. For the determination of the magnitude of dc voltage sources and a number of levels in the cascade connection, three different algorithms are proposed. The optimization of the proposed topology is aimed at achieving a higher number of levels while minimizing other parameters. A detailed comparison is made with other comparable MLI topologies to prove the superiority of the proposed structure. A selective harmonic elimination pulse width modulation technique is used to produce the pulses for the switches to achieve high-quality voltage at the output. Finally, the experimental results are provided for the basic unit with 11 levels and for cascading of two such units to achieve 71 levels at the output.

Low Switching Frequency Based Asymmetrical Multilevel Inverter Topology With Reduced Switch Count

The inceptions of multilevel inverters (MLI) have caught the attention of researchers for medium and high power applications. However, there has always been a need for a topology with a lower number of device count for higher efficiency and reliability. A new single-phase MLI topology has been proposed in this paper to reduce the number of switches in the circuit and obtain higher voltage level at the output. The basic unit of the proposed topology produces 13 levels at the output with three dc voltage sources and eight switches. Three extentions of the basic unit have been proposed in this paper. A detailed analysis of the proposed topology has been carried out to show the superiority of the proposed converter with respect to the other existing MLI topologies. Power loss analysis has been done using PLECS software, resulting in a maximum efficiency of 98.5%. Nearest level control (NLC) pulse-width modulation technique has been used to produce gate pulses for the switches to achieve better output voltage waveform. The various simulation results have been performed in the PLECS software and a laboratory setup has been used to show the feasibility of the proposed MLI topology.