Proposed Memory Structure Research Articles

DDR-MRAM: Double Data Rate Magnetic RAM for Efficient Artificial Intelligence and Cache Applications

To reduce the switching delay, area overhead, and power consumption in the magnetic tunnel junction (MTJ)-based memories, this article presents a double data rate magnetic random access memory (DDR-MRAM), which can store information at both clock levels. The proposed memory structure is such that any MTJ type (perpendicular or in-plane) and any switching method can be used as needed. The post-layout simulations based on 40 nm TSMC CMOS technology show that the proposed DDR-MRAM has at least 52% lower write PDP and at least 32% less area-to-maximum input frequency ratio than the conventional MRAMs. Monte–Carlo simulations also confirm the correct and robust operation of the proposed memory in the presence of the inevitable process variation. Moreover, based on the designed DDR-MRAM cell, three architectures are proposed to design <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$m\times n$ </tex-math></inline-formula> DDR-MRAM arrays. These architectures are designed and optimized for a specific application, including artificial intelligence (AI) hardware accelerators, high-capacity memory banks, and high-speed cache memories. The simulation results of the proposed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$m\times n$ </tex-math></inline-formula> DDR-MRAM arrays show that these arrays offer 100% higher data frequency and at least 28% less area-to-maximum input frequency ratio than the conventional MRAM arrays.

Interfacial conduction in organic ferroelectric memory diodes

Solution-processed memory diodes based on phase separated blends of ferroelectric and semiconducting polymers in the low resistance on-state operate similar to a vertical field-effect transistor at the pinch-off. Numerical simulations have shown that the performance of the diode is dominated by the conduction of charge carriers at the interface between the semiconductor and ferroelectric phases. Here, we present an unambiguous experimental demonstration of the charge injection process in the diodes. We employ a modified diode structure, wherein the electrode in contact with the semiconductor phase has been intentionally removed. Even in the absence of an electrical contact with the semiconductor phase, the diode still shows resistance switching. We provide numerical simulations that reproduce the experimentally measured I-V characteristics and therefore confirm interfacial conduction in the diodes. Furthermore, we discuss the implications of the proposed memory structure particularly in the performance of light-emitting diodes with built-in memory functionality, i.e., MEMOLEDs.

Current‐mode ultrasound beamformer with multiple‐input–sequential‐output memory structure

A current-mode ultrasound beamformer (BF) is proposed. Each channel of BF converts the echo voltage signal into current and performs uniform sampling. The sampled current of each channel is injected into one of the memory capacitors depending on a delay profile at time instance when the echo signal is sampled. Since multiple currents can be simultaneously added in parallel, multiple signal currents in parallel can be injected into one shared capacitor. By using this inherent characteristic of current-mode operation, BF of this work has a 1D memory structure unlike a 2D memory structure of other prior BFs. The proposed memory structure allows simultaneous access from multiple channels and sequential read-out operation. The proposed architecture of BF was verified by simulating an eight-channel BF using a high-voltage 0.18 μm CMOS process. Symmetric and linear delay profiles are applied to the designed BF and an output waveform of BF shows a good agreement with the derived channel gain equation. The BF consumes 220 μW/channel during receiving mode.

Partial-DNA cyclic memory for bio-inspired electronic cell

Genome memory is an important aspect of electronic cells. Here, a novel genome memory structure called partial-DNA cyclic memory is proposed, in which cells only store a portion of the system's entire DNA. The stored gene number is independent of the scale of embryonic array and of the target circuit, and can be set according to actual demand in the design process. Genes can be transferred in the cell and the embryonics array through intracellular and intercellular gene cyclic and non-cyclic shifts, and based on this process the embryonic array's functional differentiation and self-repair can be achieved. In particular, lost genes caused by faulty cells can be recovered through gene updating based on the remaining normal neighbor cells during the self-repair process. A reliability model of the proposed memory structure is built considering the gene updating method, and depending on the implementations of the memory, the hardware overhead is modeled. Based on the reliability model and hardware overhead model, we can find that the memory can achieve high reliability with relatively few gene backups and with low hardware overhead. Theoretical analysis and a simulation experiment show that the new genome memory structure not only achieves functional differentiation and self-repair of the embryonics array, but also ensures system reliability while reducing hardware overhead. This has significant value in engineering applications, allowing the proposed genome memory structure to be used to design larger scale self-repair chips.

Negative resistance element for a static memory cell based on enhanced surface generation (MOS devices)

A negative resistance (NR) element for a static memory cell using enhanced surface generation of MOS devices is proposed. Such a memory cell will maintain information with extremely small current information and the control circuitry can be the same as in one-transistor dynamic memories. The mechanism of operation is discussed and some experimental data are presented. It is shown that in order to maintain information in a single static memory cell, the required current can be as low as a few picoamperes. Operating currents are large enough to compensate for leakage currents of storage capacitors in dynamic RAM (DRAM) memories. By adding the proposed circuit in parallel with those capacitors, the dynamic memory can be converted into a static memory requiring no refresh circuit or restoring circuit. In the proposed memory structure, the storage capacitor can be reduced significantly or perhaps even eliminated. This will result in much faster operation in comparison to DRAM memories. >