Proposed Frequency Multiplier Research Articles

W‐band ×8 frequency multiplier in 65 nm CMOS with 25% bandwidth and 4.63 dBm output power

AbstractThis letter presents an ×8 frequency multiplier for the W‐band wireless satellite communication in the 65 nm complementary metal‐oxide‐semiconductor process. To reduce the power consumption, the proposed frequency multiplier employs only one driven amplifier and three stages of doublers. All doublers adopt balanced structures to increase their robustness. The output buffer is introduced to ameliorate the impedance matching of output port so that the output power of the proposed ×8 frequency multiplier can achieve 4.63 dBm. Through the special design of the interstage impedance matching circuit, the relative 3‐dB bandwidth of the proposed frequency multiplier is over 25% (from 74.8 to 96.2 GHz). The chip also has a small size and low power consumption, which is 1.37 × 0.51 mm2 and 125 mW, respectively.

A 39-GHz Frequency Tripler With >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS

The generation of the carrier signal with a very low spur level is a key challenge in all the communication systems, especially those operating at mm-waves, where a frequency multiplier is typically used to break the tradeoff between high frequency of operation and low phase noise. This letter describes a frequency tripler tailored to cover the fifth generation new radio 39-GHz frequency range. By embracing the edge-combining concept, together with the combination of a single-stage polyphase filter and a multipoint injection-locked ring oscillator, the proposed frequency multiplier is able to offer robust and consistent high harmonic rejection ratio over a large fractional bandwidth. Fabricated in 28-nm bulk CMOS technology, the measured frequency multiplier features >40-dBc harmonic rejection over an outstanding 35% fractional bandwidth, while consuming 25 mW only from 0.9-V supply. To the best of our knowledge, the proposed multiplier achieves the highest harmonic rejection among the state-of-the-art multipliers in CMOS and BiCMOS technologies, while having 60% smaller area.

A fast-lock low-power all-digital DLL-based clock generator with fractional multiple technique

In this paper, a fast-lock low-power all-digital delay-locked-loop (ADDLL)-based clock generator is proposed that generates fractional multiples of a reference frequency. The proposed clock generator comprises an ADDLL with dual-loop architecture and a fractional frequency multiplier. The coarse tune loop and fine tune loop of the proposed ADDLL can achieve a fast locking time and decrease the static phase error. Moreover, the proposed frequency multiplier can synthesize the 28-phase output clocks of the ADDLL to achieve high multiples. The experimental results demonstrated that the output frequency range of the proposed clock generator was between 176 and 224 MHz, with multiplication factors of 11 ×, 11.5 ×, 12 ×, 12.5 ×, 13 ×, 13.5 ×, and 14 × to cover the very high frequency (VHF) frequency band, where every channel had a bandwidth of 8 MHz. Moreover, the output duty cycle was close to 50% because a divider was used to generate the output signal and the lock time was less than 20 clock cycles. The clock generator was fabricated using a 0.18-μm standard CMOS process, with an active area of 0.59 mm2, power dissipation of 6.7 mW at 224 MHz, and phase noise of − 94.33 dBc/Hz with an offset of 1 MHz. Furthermore, at 176 MHz, the root-mean-square jitter was 25.01 ps, which was less than 0.45% of the output period.

High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator

A high-speed, low-power, and highly reliable frequency multiplier is proposed for a delay-locked loop-based clock generator to generate a multiplied clock with a high frequency and wide frequency range. The proposed edge combiner achieves a high-speed and highly reliable operation using a hierarchical structure and an overlap canceller. In addition, by applying the logical effort to the pulse generator and multiplication-ratio control logic design, the proposed frequency multiplier minimizes the delay difference between positive- and negative-edge generation paths, which causes a deterministic jitter. Finally, a numerical analysis is performed to analyze and compare the performance of the proposed frequency multiplier with that of previous frequency multipliers. The proposed frequency multiplier is fabricated using a 0.13- $\mu \text{m}$ CMOS process technology, and has the multiplication ratios of 1, 2, 4, 8, and 16, and an output range of 100 MHz–3.3 GHz. The frequency multiplier achieves a power consumption to a frequency ratio of 2.9 $\mu \text{W}$ /MHz.

Edge-combining multi-phase DLL frequency multiplier with reduced static phase offset and linearized delay transfer curve

An edge-combining delay-locked loop (ECDLL) frequency multiplier with multi phase outputs is presented. In contrast to architectures based on phase-locked loop, the proposed frequency multiplier pr...

기준 클럭 발생을 위한 저 젼력, 저 잡음 DLL기반 주파수 체배기

본 논문은 DLL 기술을 사용하여서 낮은 위상잡음을 갖는 주파수 체배기를 설계 하였다. VCDL은 공통모드 잡음을 줄이기 위해서 차동구조를 이용하여 설계 되었다. 이번 설계는 65nm, 1.2V TSMC CMOS 공정을 이용 하였고, 동작 주파수 범위는 10MHz에서 24MHz로 측정되었다. TCXO를 기준 주파수로 사용하여 위상잡음을 측정하였을 때 38.4MHz의 출력에서 1MHz offset 기준으로 -125dBc/Hz가 측정되었다. 총 면적은 <TEX>$0.032mm^2$</TEX>을 사용하였고, 출력 버퍼를 포함하여 총 1.8mA의 전류를 칩에서 소비하였다. This paper is designed frequency multiplier with low phase noise using DLL technique. The VCDL is designed using a differential structure to reduce common-mode noise. The proposed frequency multiplier is fabricated in a 65nm, 1.2V TSMC CMOS process, and the operating frequency range from 10MHz to 24MHz was measured. The SSB phase noise is measured to be -125dBc/Hz at 1MHz from 38.4MHz carrier. A total area of <TEX>$0.032mm^2$</TEX>were consumed in the chip, including the output buffer. Total current is 1.8mA at 1.2V supply voltage.

스위칭 모드 E급 주파수 체배기 설계

본 논문에서는 고효율 특성을 가지는 E급 주파수 체배기 설계를 제안하였다. 주파수 체배기는 2.9[㎓] 입력신호에 대하여 주파수 체배방식을 사용해 5.8[㎓] 출력신호를 얻도록 설계되어졌다.<BR> 또한 본 논문에서는 E급 주파수 체배기를 설계 및 제작하여 그 특성을 연구하였다. 측정결과, 2.9/5.8[㎓] E급 주파수 체배기는 출력전력 24.5[㏈m]에서 최대 8.5[㏈]의 변환 이득을 가지며 최대 32[%]의 고효율 특성을 보였다. 제작한 E급 주파수 체배기에 디지털 사전왜곡 선형화 기법을 적용하였다. 측정결과, 선형화 후의 출력스펙트럼은 중심주파수에서 각각 +11[㎒], +20[㎒], +30[㎒] offset인 주파수에서 적응형 선형화방식이 아닌 경우와 비교하여 12[㏈], 12[㏈], 13[㏈]의 ACPR 특성이 향상되었으며, IEEE 802.11a 무선랜 송신스펙트럼 마스크 규격을 만족하였다. 54[Mbps] 전송속도를 가지는 64-QAM 변조방식에 따른 선형화 후의 EVM은 3.83[%]로 IEEE 802.11a 송신부 EVM 규격을 만족하였다.<BR> 본 논문의 결과는 주파수 체배기를 디지털사전 왜곡 선형화를 통해 선형성과 효율성 모두를 보상할 수 있다는 것을 보여주고 있다. 주파수 체배기를 이용한 WLAN/셀룰러/PCS/WCDMA 등의 다양한 모듈 설계에 유용하게 활용 가능할 것이다.

λ/4 개방형 CRLH 스터브와 LH 전송 선로를 이용한 주파수 체배기 설계

본 논문에서는 composite right/left-handed 전송 선로를 이용한 주파수 체배기를 제안하였다. 제안된 주파수 체배기의 left-handed 전송 선로는 기본 주파수(<TEX>$f_0$</TEX>) 성분을 억압하였고, composite right/left-handed <TEX>${\lambda}/4$</TEX> 개방 스터브는 원하지 않는 고조파 신호 성분들을 제거하였다. Left-handed 전송 선로와 composite right/left-handed <TEX>${\lambda}/4$</TEX> 개방 스터브를 조합하여 사용함으로, 오직 3차 및 4차 고조파와 같은 원하는 고조파 신호들만을 효과적으로 얻을 수 있었다. 본 논문의 타당성을 보이기 위해 기본 주파수를 1 GHz로 하는 주파수 체배기를 설계하고, 측정하였다. 설계된 주파수 체배기의 입력 전력을 0 dBm으로 하였을 때, 측정된 3차 체배기와 4차 체배기의 출력 전력은 각각 -5.67 dBm과 -6.43 dBm이다. A novel frequency multiplier using composite right/left-handed transmission line is proposed. The left-handed transmission line in the proposed frequency multiplier suppresses the fundamental component(<TEX>$f_0$</TEX>), while the composite right/left-handed <TEX>${\lambda}/4$</TEX> open stub diminishes unwanted harmonics. Due to the combination of the left-handed transmission line and composite right/left-handed <TEX>${\lambda}/4$</TEX> open stub, the only desirable multiplied frequency component such as 3 <TEX>$f_0$</TEX> and 4 <TEX>$f_0$</TEX> are obtained at the output port excellently. For the example of the proposed design, frequency multipliers are designed at 1 GHz of <TEX>$f_0$</TEX> and measured. The measured output power of 3 <TEX>$f_0$</TEX> and 4 <TEX>$f_0$</TEX> is -5.67 dBm and -6.43 dBm, respectively, when the fundamental input power was 0 dBm.

Multi-Beam Velocity-Type Frequency Multiplier

One of the limitations imposed upon a conventional frequency multiplier using a double-cavity klystron is the restriction of rf output caused by the mutual repulsion of electrons. To overcome this difficulty a multibeam velocity-type frequency multiplier was proposed by the author, and theoretical and experimental investigations were made. Another type of multibeam frequency multiplier has been proposed by R. Kompfner, but as far as the author is aware, this tube has not yet been fully examined experimentally nor theoretically because of the complexity of the physical structure. Experiments made on a tentative model of the proposed frequency multiplier with two electron beams disclosed that much higher output power compared with conventional klystron multipliers could be derived. It is believed that the new tube is promising in providing a novel means of generating microwave signals of multiplied frequencies.