Proposed Fault Tolerant Strategy Research Articles

Fault tolerant control for strict-feedback nonlinear system via event-triggered adaptive algorithms

In this paper, the event-triggered adaptive fault tolerant tracking control for the strict-feedback nonlinear system with mismatched unknown parameters, external disturbances and actuator faults is addressed. A novel adaptive fault tolerant mechanism is presented to overcome the difficulty arising from the actuator faults and mismatched parameters, where the parameters estimators are generated from discrete state governed by the state dependent event-triggered mechanism. Furthermore, by introducing the auxiliary dynamic, it is shown that all the signals of the system are ultimately bounded and the asymptotical output tracking error is within a small residual set including origin which can be modified arbitrarily small by tuning the control coefficients. Based on the presented adaptive fault tolerant mechanism, the robust event-triggered mechanism and adaptive algorithm are further developed and the boundedness of all the variables of the system is shown. What is more, it is proved that both of the presented event-triggered mechanisms are Zeno-free. Finally, the control effectiveness of the proposed fault tolerant strategy is discussed and verified by a numerical example and the single-link manipulator.

Fault Tolerant Lanczos Eigensolver via an Invariant Checking Method

An extensive survey of the literature shows that the Lanczos eigensolver is a popular iterative method for approximating a few maximal eigenvalues of a real symmetric matrix, particularly if the matrix is large and sparse. In recent years, graphics processing units (GPUs) have become a popular platform for scientific computing applications, many of which are based on linear algebra, and are increasingly being used as the main computational units in supercomputers. This trend is expected to continue as the number of computations required by scientific applications reach petascale and exascale range. In this paper, building on our earlier work [22], we investigate in detail the error checking mechanism for the Lanczos eigensolver. We identify a low cost invariant for efficient error checking, and through mathematical analysis determine the efficiency of our mechanism when used by the Lanczos eigensolver. We evaluate the proposed fault tolerant scheme using an open-source sparse eigensolver on a GPU platform, with and without the injection of faults. We use a large number of sparse matrices from real applications, to determine the efficiency and efficacy of our method and our implementation shows that the proposed fault tolerant method has good error coverage and low overhead. To the best of our knowledge, we are the first to introduce such a scheme for the Lanczos method.

Fault-Tolerant Space Vector Modulation for Modular Multilevel Converters With Bypassed Faulty Submodules

This paper develops a modulation based fault-tolerant (FT) strategy for restoring the operation of three-phase modular multilevel converters (MMCs) with faulty switches. This FT strategy is based on a proposed modified space vector modulation (SVM) technique that generates balanced line-to-line (line) voltages even in the case of a fault occurrence. In the postfault operation, the proposed strategy is able to restore the fundamental amplitude of the line to the neutral (load) voltages to that of the normal operation condition with a slightly increased voltage stress over the switches in the faulty phase. In this paper, first a brief background about MMCs and SVM technique is provided. Then, the proposed FT strategy and the modified SVM technique are presented. Finally, several simulation and experimental results are provided to validate operation of the proposed strategy.

Reliability improvement of transistor clamped H‐bridge‐based cascaded multilevel inverter

Reduced voltage stress and low-total harmonic distortion are the main causes for such widespread application of multilevel inverters (MLIs) in various industrial sectors. However, reliability is one of the major concerns of MLIs as it uses a large number of switches as compared with two-level inverters. Therefore, a newly developed transistor clamped H-bridge inverter is proposed in the literature which uses a relatively less number of switches and DC sources as compared with cascaded H-bridge but lacks in reliability due to the absence of redundant states. Hence, in this study, the reliability improvement strategy for newly developed five-level transistor clamped H-bridge-based cascaded inverter is proposed which can be generalised for any number of levels. In the proposed fault tolerant strategy, the fault can be broadly classified based on the two main legs of the proposed inverter. Moreover, the proposed fault tolerant strategy does not require any kind of external circuit for maintaining its capacitor voltage in the balanced state. Finally, to validate the concept, a laboratory prototype of the five-level inverter is developed and results are obtained successfully.

A fault tolerant strategy for multilevel dc-dc converters to improve the PV system efficiency

The main idea of this paper is to study a photovoltaic energy conversion chain for the production of electrical energy on isolated sectors with control, faults diagnostic and reconfiguration of the used Three-level boost converter. A method for the control of Three-level boost converter was proposed to achieve three goals: to track the PV maximum power point (MPPT), to ensure the voltage balance and to regulate the DC link voltage. Further, in order to maintain the operation of the PV chain, detection, localization and reconfiguration methodology of open circuit fault, which might occur due to a failure of one power switch of the Three-level boost converter, is proposed. Finally, simulation investigations under Matlab/Simulink environment were performed to check the effectiveness, feasibility and reliability of the proposed fault tolerant strategy.

Active Fault Tolerant Decentralized Control Strategy for an Autonomous 2WS4WD Electrical Vehicle Path Tracking

This paper presents an active fault tolerant control (AFTC) strategy for preserving the path tracking for an autonomous 2 wheel-steering 4 wheel-driving (2WS4WD) electrical vehicle in the presence of an actuator fault. It is based on a decentralized fault tolerant control strategy for overactuated systems. The strategy consists of generating new REFERENCEs for redundant actuators, which are only used when faults are detected, and tracking these REFERENCEs. For a 2WS4WD vehicle, five actuators are used in normal situations to ensure the vehicle path tracking: the front-wheel steering actuator and the four traction actuators. However, in faulty situations, the vehicle's rear-wheel steering actuator is controlled in order to preserve the system's path tracking and to ensure the desired performance. The elaborated control law that is used to control the rear-wheels steering system is composed of 2 interconnected control loops: an outer loop and an inner loop. This decentralized control strategy tolerates the traction and the front-wheel steering actuator faults. The main advantage of the proposed fault tolerant strategy is that the faults can be compensated by computing online new REFERENCEs for the control loops without changing the initial controllers. This strategy provides the necessary time for a diagnosis system to precisely isolate the faulty actuator. This method is tested and validated on a realistic vehicle dynamic model co-simulated using CarSim and Matlab-Simulink softwares.

Fault-tolerant control based Super-Twisting algorithm for the diesel engine air path subject to loss-of-effectiveness and additive actuator faults

In this paper, a passive fault tolerant control strategy carried out under the concept of higher order sliding mode control is developed for the diesel engine air path. The proposed fault tolerant strategy incorporates a Super-Twisting algorithm controller which handles parametric uncertainties and actuator faults. In this paper we consider two types of actuator faults, additive and loss-of-effectiveness faults. Theoretical results on the convergence of the proposed controller based on the Lyapunov theory are presented. The simulations of the proposed controller on a recently validated experimental air path diesel engine model show good results under actuator faults conditions even in the presence of parametric uncertainties.

Passive Fault-Tolerant Control for the Diesel Engine Air Path Subject to Loss-of-Effectiveness and Additive Time Varying Actuator Faults

In this paper we developed a passive fault tolerant control strategy for the diesel engine air path. This strategy is carried out under the concept of Higher Order Sliding Mode Control (HOSMC). The proposed fault tolerant strategy incorporates a super twisting controller which handles parametric uncertainties and actuator failures. In this paper we consider two types of actuator failures, additive and loss-of-effectiveness faults. The simulations of the proposed controller on a recently validated experimental air path diesel engine model, show good results for actuator failures conditions even in the presence of uncertainties on model parameters.

Replication based fault tolerant job scheduling strategy for economy driven grid

In this paper, the problem of fault tolerance in grid computing is addressed and a novel adaptive task replication based fault tolerant job scheduling strategy for economy driven grid is proposed. The proposed strategy maintains fault history of the resources termed as resource fault index. Fault index entry for the resource is updated based on successful completion or failure of an assigned task by the grid resource. Grid Resource Broker then replicates the task (submitting the same task to different backup resources) with different intensity, based on vulnerability of resource towards faults suggested by resource fault index. Consequently, in case of possible fault at a resource the results of replicated task(s) on other backup resource(s) can be used. Hence, user job(s) can be completed within specified deadline and assigned budget, even on the event of faults at the grid resource(s). Through extensive simulations, performance of the proposed strategy is evaluated and compared with the Time Optimization and Checkpointing based Strategy in an economy driven grid environment. The experimental results demonstrate that in the presence of faults, proposed fault tolerant strategy improves the number of tasks completed with varied deadline and fixed budget as well as number of tasks completed with varied budget and fixed deadline. Additionally, the proposed strategy used a smaller percentage of deadline time as compare to both Time Optimization and Checkpointing based Strategy. Although the proposed strategy has a percentage of budget spent greater than that of Time Optimization Strategy and Checkpointing based Strategy, it is accepted as a proposed strategy in time optimization where the main objective is to maximize tasks completed within a given deadline. It can be concluded from the experiments that the proposed strategy shows improvement in satisfying the user QoS requirements. It can effectively schedule tasks and tolerate faults gracefully even in the presence of failures, but the costs are slightly higher in terms of budget consumption. Hence, the proposed fault tolerant strategy helps in sustaining user's faith in the grid, by enabling the grid to deliver reliable and consistent performance in the presence of faults.

데이터 전송 오류에 대한 고장 극복 암호회로

This paper presented a solution to encryption and decryption problem suffering data transmission error for encrypted message transmission. Block cypher algorithms experience avalanche effect that a single bit error in an encrypted message brings substantial error bits after decryption. The proposed fault tolerant scheme addresses this error avalanche effect exploiting a multi-dimensional data array shuffling process and an error correction code. The shuffling process is to simplify the error correction. The shuffling disperses error bits to many data arrays so that each n-bit data block may comprises only one error bit. Thereby, the error correction scheme can easily restore the one bit error in an n-bit data block. This scheme can be extended on larger data blocks.