Proposed Electrostatic Discharge Protection Circuit Research Articles

Study on ESD Protection Circuit by TCAD Simulation and TLP Experiment

The anti-ESD characteristic of the electronic system is paid more and more attention. Moreover, the on-chip electrostatic discharge (ESD) is necessary for integrated circuits to prevent ESD failures. In this paper, the mixed TCAD model of the ESD protection circuit is built and simulated, and the negative transmission line pulse (TLP) injection damage experiment is carried out on the CD4069UBC chip. The circuit model consists of three-dimensional shallow trench isolation (STI) diode TCAD models and a three-dimensional multi-gate Complementary Metal-Oxide-Semiconductor (CMOS) inverter TCAD model. Moreover, the TCAD modeling is based on a 0.25 μm technology node. Through the transient simulation of the electrothermal coupling, the electrical signal of the input and output nodes of the circuit and the distribution of the electrothermal parameters in the device are obtained. Moreover, by analyzing the simulation results, the physical phenomena and the mechanisms of interference and damage mechanism during TLP injection are explained. The location and type of diode damage in the TLP injection simulation results of the circuit model are consistent with the TLP experiment damage results. The proposed ESD protection circuit model and analysis method are beneficial to ESD robustness prediction and ESD soft damage analysis of IC.

Design of LDO Regulator With High Reliability ESD Protection Circuit Using Analog Current Switch Structure for 5-V Applications

The modern electronic device should be able to provide stable voltage and current under a variety of conditions. The LDO regulator used in the electronic device is a system that requires various voltages and load currents. This paper suggests to the LDO regulator with the high reliability ESD protection circuit that achieves low peak voltage through analog switch structure. The proposed LDO regulator has the function of detecting the output voltage fluctuations depending on the load via an analog switch structure and effectively controlling the peak voltage. In addition, as IC is miniaturized and integrated, circuit failures frequently occur in mobile devices using the low voltage due to electrostatic discharge (ESD). The proposed ESD protection circuit is placed on I/O and power lines to prevent the IC circuit from being destroyed from the inevitable ESD phenomenon. Therefore, in this paper, an ESD protection circuit was built into the LDO regulator to verify high reliability from ESD situations. It was verified that the high reliability of the IC can be improved through effective current discharge due to ESD surge. The proposed LDO regulator, implemented in a 0.13μm BCD process, achieves an undershoot voltage of 25 mV and an overshoot voltage of 28 mV for a load current of 300 mA.

All-directional Electrostatic-discharge Protection Circuit with High Area-efficiency

This paper proposes a design for a wholechip all-directional electrostatic-discharge (ESD) protection circuit using a resistor-capacitor (RC) lateral insulated-gate bipolar transistor (LIGBT)-based 12 V power clamp and a silicon-controlled rectifier (SCR)-based 12 V input/output (I/O) clamp. The RC LIGBT-based power clamp detects pulses through an ESD detection circuit and applies a bias to the gate. Therefore, the proposed power clamp does not have snapback curve and has a low impedance during an ESD event. In addition, the structural characteristics of the proposed I/O clamp enable it to provide discharge paths for all four ESD discharge modes (PS, PD, NS, ND), and the clamp is more area efficient than conventional ESD protection circuits composed of gate-grounded n-type metal-oxide-silicon transistors or SCRs. Moreover, because floating regions are inserted in the I/O clamp and the clamp has a high holding voltage, the clamp design is resistant to latch-up, which is a critical drawback of snapback devices. Therefore, the proposed ESD protection circuit can effectively provide highly reliable protection to internal integrated circuits. The proposed circuit was fabricated using a 0.18 ㎛ bipolar-CMOS-DMOS process, and the electrical properties and ESD robustness of the circuit were verified through a transmission line pulse measurement method and human body model surge application tests.

Silicon-controlled Rectifier-based Electrostatic Discharge Protection Circuit with Additional NPN Parasitic Bipolar Junction Transistor for 5-V Application

This paper proposes a novel protection circuit based on a silicon-controlled rectifier (SCR) to prevent electrostatic discharge (ESD) at low voltages. The proposed device consists of an additional NPN parasitic bipolar transistor operated via application of an N+ diffusion region and a well breakdown voltage, to reduce the high trigger voltage caused by the well breakdown voltage of the existing SCR structure. Furthermore, the proposed device exhibits an improved trigger voltage, holding voltage, and dynamic resistance component when compared with existing parasitic PNP bipolar transistors. The proposed ESD protection circuit was manufactured using a 0.18 μm bipolar-CMOS-DMOS; it exhibited a significant improvement in electrical characteristics such as trigger voltage (8.1 V) and holding voltage (3.55 V), according to the results of transmission line pulse measurement. Hence, it is deemed to be suitable for 5-V-class applications.

ESD protection circuit for V-band RF applications in a 65nm CMOS technology

To apply radio frequency circuits, nanoscale CMOS technologies are greatly used but this consequence to a thinner gate oxide and silicided drain/source. With this, the electrostatic discharge (ESD) robustness of RF circuits will be much more degraded. Therefore, there is a need for an ESD protection circuit design in RF circuits against ESD damages. In this paper, the proposed ESD protection circuit is presented with concept based silicon-controlled rectifier (SCR) device, two diodes, PMOS transistor and an inductor to efficiently provide protection for radio-frequency (RF) circuits from ESD damages in nanoscale CMOS process. The concept based SCR device is aided with an inductor to provide efficient ESD path discharge to the SCR device. Moreover, the inductor is used to resonate out the parasitic capacitance generated by the ESD protection circuit at the preferred frequency. In addition, the proposed ESD protection circuit is implemented to a low noise amplifier (LNA) at 60-GHz frequency within an efficient area. Furthermore, the ESD protection circuit is simulated to achieve over 2-kV human body model ESD robustness with good RF performances on LNA in 65-nm CMOS technology.

Study on 4H-SiC GGNMOS Based ESD Protection Circuit With Low Trigger Voltage Using Gate-Body Floating Technique for 70-V Applications

In this letter, we propose a 4H-SiC-based electrostatic discharge (ESD) protection circuitwith a new structure that has low on-resistance and good high-temperature characteristics while improving the high triggering voltage by applying an improved floating technology to the 4H-SiC grounded-gate n-type metal-oxide-semiconductor (GGNMOS) for 70-V applications. Electrical characteristics of the 4H-SiC-based conventional GGNMOS, floating-body NMOS, and the proposed ESD protection circuit were compared and analyzed using the transmission-line pulse test. To verify the high-temperature characteristics of the proposed 4H-SiC-based ESD protection circuit, its thermal reliability was measured at high temperatures (300-500 K).

On-Chip HBM and HMM ESD Protection Design for RF Applications in 40-nm CMOS Process

On-chip electrostatic discharge (ESD) protection device with large dimension can sustain high-ESD current, but the parasitic capacitance of the ESD protection device will increase the difficulty of impedance matching and degrade the bandwidth for broadband radio frequency (RF) applications. The traditional distributed ESD protection circuit can achieve good impedance matching, but it has a worse ESD robustness because of larger resistance caused by the input inductor. In this paper, a new distributed ESD protection structure with the stacked diodes with embedded silicon-controlled rectifier is proposed to attain good ESD robustness without degrading the RF performance. The proposed ESD protection circuit has been successfully verified in a 40-nm, 2.5-V CMOS process to sustain a human-metal model of 5 kV. The proposed ESD protection circuit is suitable to protect the broadband RF circuits in advanced nanoscale CMOS technology.

Low Ron and high robustness ESD protection design for low‐voltage power clamp application

An electrostatic discharge (ESD) protection circuit with novel structure based on a silicon-controlled rectifier (SCR) is proposed for 5 V ESD protection of integrated circuits. The proposed ESD protection circuit has large current driving capacity due to its low on-resistance and high ESD robustness in comparison with the conventional SCR-based ESD protection circuit. The conventional SCR-based ESD protection circuit and the proposed ESD protection circuit were fabricated using a 0.18 µm bipolar CMOS-double diffused metal-oxide semiconductor transistor (DMOS) process, and their electrical characteristics and ESD robustness were comparatively analysed using transmission line pulse measurements.

The Analysis of SCR-Based ESD Protection Circuit with P-Drift and N+ Floating Region

In this paper, a novel SCR (Silicon Controlled Rectifier)-based ESD(Electrostatic Discharge) protection circuit for power clamp is proposed. The proposed protection circuit has high holding voltage due to floating n+ region which reduces current gain of parasitic bipolar transistor. This characteristic makes it ensure latch-up immunity. The electrical characteristics of the proposed ESD protection circuit have been simulated by using Synopsys TCAD simulation tool. According to the simulation results, the proposed protection circuit has high holding voltage of about 4.61V to 8.75V as design variation. Also, it is verified by using TLP (Transmission Line Pulse) system. As a result of measurement, it has holding voltage of 15.7V to 19.35V as design variation and high robustness above HBM 6kV, MM 600V.

파워 클램프용 래치-업 면역 특성을 갖는 SCR 기반 ESD 보호회로

In this paper, SCR(Silicon Controlled Rectifier)-based ESD(Electrostatic Discharge) protection circuit for power clamp is proposed. In order to improve latch-up immunity caused by low holding voltage of the conventional SCR, it is modified by inserting n+ floating region and n-well, and extending p+ cathode region in the p-well. The resulting ESD capability of our proposed ESD protection circuit reveals a high latch-up immunity due to the high holding voltage. It is verified that electrical characteristics of proposed ESD protection circuit by Synopsys TCAD simulation tool. According to the simulation results, the holding voltage is increased from 4.61 V to 8.75 V while trigger voltage is increased form 27.3 V to 32.71 V, respectively. Compared with the conventional SCR, the proposed ESD protection circuit has the high holding voltage with the same triggering voltage characteristic.

ESD 보호 소자를 탑재한 Peak Current-mode DC-DC Buck Converter

In this paper, dc-dc buck converter controled by the peak current-mode pulse-width-modulation (PWM) presented. Based on the small-signal model, we propose the novel methods of the power stage and the systematic stability designs. To improve the reliability and performance, over-temperature and over-current protection circuits have been designed in the dc-dc converter systems. To prevent electrostatic An electrostatic discharge (ESD) protection circuit is proposed. The proposed dc-dc converter circuit exhibits low triggering voltage by using the gate-substrate biasing techniques. Throughout the circuit simulation, it confirms that the proposed ESD protection circuit has lower triggering voltage(4.1V) than that of conventional ggNMOS (8.2V). The circuit simulation is performed by Mathlab and HSPICE programs utilizing the 0.35um BCD (Bipolar-CMOS-DMOS) process parameters.

Design of Dual-Band ESD Protection for 24-/60-GHz Millimeter-Wave Circuits

To effectively protect the millimeter-wave (MMW) circuits in nanoscale CMOS technology from electrostatic discharge (ESD) damages, a dual-band ESD protection cell for 24-/60-GHz ESD protection is presented in this paper. The proposed ESD protection cell consisted of a diode, a silicon-controlled rectifier, a PMOS, and two inductors. To verify the dual-band characteristics and ESD robustness, the proposed ESD protection circuit had been applied to a 24-/60-GHz low-noise amplifier (LNA). The measurement results showed over-2-kV human-body-model ESD robustness with little performance degradation on LNA. The proposed dual-band ESD protection cell was suitable for circuit designers for them to easily apply ESD protection in the dual-band MMW circuits.

Large-Swing-Tolerant ESD Protection Circuit for Gigahertz Power Amplifier in a 65-nm CMOS Process

The signal swing at output pad of some radio-frequency (RF) power amplifiers (PAs) may be higher than the supply voltage. To protect the gigahertz large-swing power amplifier from electrostatic discharge (ESD) damage in nanoscale CMOS process, a large-swing-tolerant ESD protection circuit is presented in this paper. The proposed ESD protection circuit had been designed, fabricated, and characterized in a 65-nm CMOS process, where it can achieve low parasitic capacitance, large swing tolerance, high ESD robustness, and good latchup immunity. The proposed ESD protection circuit had been further applied to a 2.4-GHz PA to provide 3-kV human-body-model (HBM) ESD robustness without degrading the RF performances.

Improvement of Electrostatic Discharge Protection by Introducing a Spindt-Type Silicon Field Emission Device

In this paper, an original Spindt-type silicon field emission device (FED) with electrostatic discharge (ESD) regulation capability is proposed. The fabricated FED characteristics, including process parameters, capacitance–voltage (C–V), current–voltage (I–V), and frequency response, are investigated. To verify its capability of ESD protection, we replace the metal oxide varistor (MOV) in a state-of-the-art protection configuration with the fabricated FED under the application conditions of system-level ESD tests. The measured results show that the proposed ESD protection circuit composed of a prestage gas arrestor, an intermediate resistor, and an introduced FED can suppress an injected ESD pulse voltage of 6000 to 3193 V, a reduction of 46.8%, whereas suppression is to 5606 V, a reduction of 6.57%, when using only a gas arrestor.

Design of ESD protection device using body floating technique in 65 nm CMOS process

A floating body electrostatic discharge (ESD) protection circuit positioned between and coupled to an I/O pad and an internal circuit is presented. A small NMOS transistor is used to control the body of a main NMOS transistor. When the small NMOS transistor is triggered, the body of the main NMOS transistor remains grounded. If the small NMOS transistor has not been triggered, the body of the main NMOS transistor remains in a floating state, lowering the range of the snapback voltage. As a consequence the ESD protection circuit is able to function more rapidly. The proposed ESD protection circuit is designed in 65 nm CMOS technology.

Decreasing-size distributed ESD protection scheme for broad-band RF circuits

The capacitive load, from the large electrostatic discharge (ESD) protection device for high ESD robustness, has an adverse effect on the performance of broad-band RF circuits due to impedance mismatch and bandwidth degradation. The conventional distributed ESD protection scheme using equal four-stage ESD protection can achieve a better impedance match, but degrade the ESD performance. A new distributed ESD protection structure is proposed to achieve both good ESD robustness and RF performance. The proposed ESD protection circuit is constructed by arranging ESD protection stages with decreasing device size, called as decreasing-size distributed electrostatic discharge (DS-DESD) protection scheme, which is beneficial to the ESD level. The new proposed DS-DESD protection scheme with a total capacitance of 200 fF from the ESD diodes has been successfully verified in a 0.25-/spl mu/m CMOS process to sustain a human-body-model ESD level of greater than 8 kV.

ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit

A substrate-triggered technique is proposed to improve the electrostatic discharge (ESD) robustness of a stacked-nMOS device in the mixed-voltage I/O circuit. The substrate-triggered technique can further lower the trigger voltage of a stacked-nMOS device to ensure effective ESD protection for mixed-voltage I/O circuits. The proposed ESD protection circuit with substrate-triggered design for a 2.5-V/3.3-V-tolerant mixed-voltage I/O circuit has been fabricated and verified in a 0.25-/spl mu/m salicided CMOS process. The substrate-triggered circuit for a mixed-voltage I/O buffer to meet the desired circuit application in different CMOS processes can be easily adjusted by using HSPICE simulation. Experimental results have confirmed that the human- body-model (HBM) ESD robustness of a mixed-voltage I/O circuit can be increased /spl sim/60% by this substrate-triggered design.

On-Chip ESD Protection Design With Substrate-Triggered Technique for Mixed-Voltage I/O Circuits in Subquarter-Micrometer CMOS Process

A new electrostatic discharge (ESD) protection design, by using the substrate-triggered stacked-nMOS device, is proposed to protect the mixed-voltage I/O circuits of CMOS ICs. The substrate-triggered technique is applied to lower the trigger voltage of the stacked-nMOS device to ensure effective ESD protection for the mixed-voltage I/O circuits. The proposed ESD protection circuit with the substrate-triggered technique is fully compatible to general CMOS process without causing the gate-oxide reliability problem. Without using the thick gate oxide, the new proposed design has been fabricated and verified for 2.5/3.3-V tolerant mixed-voltage I/O circuit in a 0.25-/spl mu/m salicided CMOS process. The experimental results have confirmed that the human-body-model ESD level of the mixed-voltage I/O buffers can be successfully improved from the original 3.4 to 5.6 kV by using this new proposed ESD protection circuit.

Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers

A new electrostatic discharge (ESD) protection circuit, using the stacked-nMOS triggered silicon controlled rectifier (SNTSCR) as the ESD clamp device, is designed to protect the mixed-voltage I/O buffers of CMOS ICs. The new proposed ESD protection circuit, which combines the stacked-nMOS structure with the gate-coupling circuit technique into the SCR device, is fully compatible to general CMOS processes without causing the gate-oxide reliability problem. Without using the thick gate oxide, the experimental results in a 0.35 /spl mu/m CMOS process have proven that the human-body-model ESD level of the mixed-voltage I/O buffer can be successfully increased from the original /spl sim/2 kV to >8 kV by using this proposed ESD protection circuit.

A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS ICs

A novel electrostatic discharge (ESD) protection circuit, which combines complementary low-voltage-triggered lateral SCR (LVTSCR) devices and the gate-coupling technique, is proposed to effectively protect the thinner gate oxide of deep submicron CMOS ICs without adding an extra ESD-implant mask. Gate-coupling technique is used to couple the ESD-transient voltage to the gates of the PMOS-triggered/NMOS-triggered lateral silicon controlled rectifier (SCR) (PTLSCR/NTLSCR) devices to turn on the lateral SCR devices during an ESD stress. The trigger voltage of gate-coupled lateral SCR devices can be significantly reduced by the coupling capacitor. Thus, the thinner gate oxide of the input buffers in deep-submicron low-voltage CMOS ICs can be fully protected against ESD damage. Experimental results have verified that this proposed ESD protection circuit with a trigger voltage about 7 V can provide 4.8 (3.3) times human-body-model (HBM) [machine-model (MM)] ESD failure levels while occupying 47% of layout area, as compared with a conventional CMOS ESD protection circuit.