Design of ESD protection device using body floating technique in 65 nm CMOS process

Abstract

A floating body electrostatic discharge (ESD) protection circuit positioned between and coupled to an I/O pad and an internal circuit is presented. A small NMOS transistor is used to control the body of a main NMOS transistor. When the small NMOS transistor is triggered, the body of the main NMOS transistor remains grounded. If the small NMOS transistor has not been triggered, the body of the main NMOS transistor remains in a floating state, lowering the range of the snapback voltage. As a consequence the ESD protection circuit is able to function more rapidly. The proposed ESD protection circuit is designed in 65 nm CMOS technology.