Proposed Cache Scheme Research Articles

New Collaborative Caching Scheme for D2D Content Sharing in 5G

Device-to-Device (D2D) content sharing is an excellent solution to offload the traffic from the core 5G networks and backhaul links. Caching the most popular files at the network edge and in users’ devices to support user proximity services in 5G helps to offload traffic in the core network and increases the cache hit probability. D2D communication in 5G can be utilized to share the cached files between a pair of devices with a minimal involvement from the base station. This paper presents a collaborative content caching scheme with the primary objective to maximize the overall system offloading gain and the cache hit probability in downloading the popular file contents. The proposed system model exploits the social-networking concept within the WiFi Direct radio range, assuming the cell structure present in a densely populated area such as a university campus or an auditorium. The performance of the proposed cache scheme is evaluated through extensive simulations taking into consideration the device mobility and disconnection, and the results are presented.

A Buffered Dual-Access-Mode Scheme Designed for Low-Power Highly-Associative Caches

This paper proposes a buffered dual-access-mode cache to reduce power consumption for highly-associative caches in modern embedded systems. The proposed scheme consists of a MRU (most recently used) buffer table and a single cache structure to implement two accessing modes, phased mode and way-prediction mode. The proposed scheme shows better access time and lower power consumption than two popular low-power caches, phased cache and way-prediction cache. The authors used Cacti and SimpleScalar simulators to evaluate the proposed cache scheme by using SPEC benchmark programs. The experimental results show that the proposed cache scheme improves the EDP (energy delay product) up to 40% for instruction cache and up to 42% for data cache compared to way-prediction cache, which performs better than phased cache.

Cached SLM to reduce the PAPR of OFDM signal

Selected mapping (SLM) is one of the most well-known peak-to-average power ratio (PAPR) reduction techniques proposed for the orthogonal frequency-division multiplexing (OFDM) systems. The main drawback of the conventional SLM scheme is high computational complexity because of numerous inverse fast fourier transform (IFFT) operations when transmitting one OFDM signal, which may hinder its wide application in certain systems. The aim of this paper is to propose a post-IFFT PAPR reduction scheme based on a cache structure. in the proposed scheme, several candidates are created through combining two of time-domain signal vectors in cache and the one with the lowest PAPR is transmitted. Because the generation of candidates is implemented after the IFFT, one OFDM signal only requires one complex IFFT operation when using the proposed cache scheme. simulation results show that the new proposed scheme has promising PAPR performance while it decreases the complexity compared with the conventional SLM scheme. In addition, the cache scheme has the ability to be combined with other scheme such as SLM to further reduce the PAPR at the cost of a moderate increase of the complexity. Copyright © 2012 John Wiley & Sons, Ltd.

Design of an adjustable‐way cache for energy reduction

Conventional set‐associative caches, with higher associativity, provide lower miss rates. However, they suffer from longer hit access time and larger energy dissipation. Based on the consideration of different program localities, programs should have their own appropriate associativity of caches. In this paper, we propose a set‐associative cache that can provide flexibilities to adjust its associativity according to different program behaviors, which means that the proposed cache scheme can be adjusted from an n‐way set‐associative cache to a direct‐mapped cache. By use of this cache architecture, power consumption can be lowered when an n‐way set‐associative cache configures the cache with lower associativity (less than n) due to only enabling fewer subarrays of the tag memory and data memory. However, the performance is still maintained at the same level as in a conventional set‐associative cache or direct‐mapped cache. Adjustable‐way set‐associative caches can also be applied to multiprocessor systems to reduce the average, overall system, energy dissipation.