Proposed Cache Design Research Articles

An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs

The STT-MRAM technology is a promising candidate for future on-chip cache memory because of its high density, low standby power, and nonvolatility. As the technology node scales, especially under 40-nm technology node, STT-MRAM cell design becomes a key issue to approach low power consumption, high access performance, and desirable reliability. The conventional 1T-1 magnetic tunnel junction (MTJ) and 2T-2MTJ cell designs cannot address these challenges efficiently. In this paper, we propose a novel 3T-3MTJ cell structure using the advanced perpendicular MTJ (p-MTJ) technology. It can store 2 bits with three MTJs. The differential sensing technique can be used to read out the most significant bit as fast as the 2T-2MTJ design. The sensing latency of 2 bits within the same cell is almost the same as the sensing latency of the 1T-1MTJ cell design. Therefore, the 3T-3MTJ cell can have the advantages of both 2T-2MTJ and 1T-1MTJ cells. Circuit-level simulations show that the proposed 3T-3MTJ cell structure can achieve a desirable tradeoff between storage density, access performance, and energy consumption compared to the prior 1T-1MTJ and 2T-2MTJ cell structures. Additionally, we propose a novel adaptive cache design based on the 3T-3MTJ cell structure, which can work in different modes to satisfy various memory access demands from different applications. Architecture level simulations validate the effectiveness of the proposed cache design.

AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture

Spin-transfer torque magnetic RAM (STT-MRAM) is a promising memory technology for lower level caches because of its high density and nonvolatile nature. However, the high write latency is a bottleneck to its widespread adoption as the future on-chip memory. In this paper, we propose a new cache architecture-asymmetric write architecture with redundant blocks (AWARE)-that can improve the write latency by taking advantage of the asymmetric write characteristics of 1T-1MTJ STT-MRAM bit-cells. Due to the nature of the storage element in STT-MRAM, the time required for the two-state transitions ( 1→ 0 and 0→ 1) is not identical. In other words, one of the state transitions is slower than the other direction. In conventional cache architecture, the overall write latency is limited by the slower transition. However, the AWARE cache design introduces redundant blocks in each row, and they are preset to the initial state that enables the faster transition. Hence the write operations performed in these redundant blocks are much faster than the conventional write scheme. The write latency in AWARE is improved by 30% over conventional cache architecture with no area penalty in the data array. Moreover, the additional tag bits introduced in this technique result in penalty on the total cache area. In addition, the write energy increases modestly by 7% in the proposed cache design. However, this write-energy increase can be mitigated by sacrificing the cache capacity.

Run-Time Reconfiguration of Expandable Cache for Embedded Systems

Expandable cache proposed by Bournoutian and Orailoglu is very efficient in reducing miss rate and energy consumption with small area overhead. However, the original expandable cache with only one expansion scheme may lead to thrashing problems. In this work, based on the structure of expandable cache, we will introduce a new cache design which has many expansion schemes to fit different run-time program behaviors. The expansion scheme of our proposed cache is dynamically changed by executing configuration instructions which are inserted at compile time. The experimental results of SPEC CPU2000 have shown that our proposed cache design effectively improves the miss rate by 14.74% as compared with the original expandable cache. In terms of energy improvement ratio, our method is 5.62% higher than that of expandable cache when the baseline is set as the energy consumption of 2-way set-associative cache.