Properties Of Low-k Materials Research Articles

Finite element analysis of multi-level interconnection under cyclic thermomechanical loads

In manufacturing processing, using copper wire for connecting each micro-device and constructing logical circuit to reduce RC time delay is a major technique. However, during fabrication, the thermo-mechanical mismatch between materials generate high stress, which lead to stress-induced voids, cracks, and interface delamination, all of which we strongly affect the reliability of integrated circuits. This study utilizes materials mechanics, fracture mechanics, and the finite element method to analyze cracking and interfacial delamination of thin films and interconnect structures and to determine the strain energy release rate within such structures under cyclic thermal loading. In addition, parametric studies that analyze the influence of each physical parameter (e.g., temperature, geometry, and properties of low-k materials) on the stress, strain energy release rate, and crack growth. Based on these investigations, we optimize size parameters of the interconnect structure. The results show that mismatch of thermo-mechanical behavior between different materials and spaces on wires are significant factors for generating high stresses. It is also found that selecting the low-k materials with higher Young’s modulus and lower coefficient of thermal expansion can avoid caused high stress. The temperature range is on focus improve the reliability of interconnect structures, and variations energy release rate could prevent interfacial delamination of thin films.

Material and Structure Designs for Reliable Quad-Flat-Package for Scaled-Down Ultralarge-Scale Integrations With Porous Low-$k/{\rm Cu}$ Interconnects

Reliability of a quad-flat-package (QFP) with a circuit-under-pad (CUP) structure is investigated for Cu interconnects with porous low dielectric constant (low-k) films in scaled-down ultralarge-scale integrations. The following experimental factors are discussed: 1) low-k material properties and their stacking structures; 2) CUP structure; and 3) mold compound material properties. The QFP characteristics are analyzed after chip dicing and Ag wire bonding, as well as after molding. Higher adhesion strength of porous low-k film to SiCN cap dielectrics and rigid Cu-anchored CUP structure can achieve highly reliable QFP packaging. A lower coefficient of thermal expansion (CTE) of the molding compound is also found to be effective in eliminating low-k delamination during thermal cycle test because it can reduce the stress at the cracking position. The adhesion-promoting porous SiOCH film with the Cu-anchored CUP in a low-CTE mold is a promising system to realize a reliable QFP with no low-k delamination, passing electrical tests after the pressure-cooker test and high-temperature storage test.

Characterization of thermal treatment effects on thermal and electrical stability of low-k material

The effect of thermal treatments on the stability of electrical/physical properties of low-k materials was investigated. A organosilicate thin film with a dielectric constant of around 3 was deposited by plasma enhanced chemical vapor deposition (PECVD) using diethoxymethylsilane (DEMS™) precursor and oxygen gas. Thermal curing was performed at 300 °C to 700 °C in steps of 50 °C. Annealing phenomena at 400 °C were thoroughly studied. After thermal treatment, thickness shrinkage and refractive index variations were negligible up to 500 °C. At 700 °C, however, the thickness decreased by 23 %, and the refractive index decreased by 2.78 %. The electrical property was characterized by capacitance-voltage measurements using a metal-low-k dielectric-semiconductor structure. The k-value obtained from as-deposited samples was derived as 2.88, stable up to 400 °C, but decreasing to 2.4 after annealing at 500 and 600 °C. At higher temperatures, the k-value increased to above 5. Such a trend can be explained by the degradation of the organosilicate structure due to thermal stress. FTIR characterization indeed revealed a loss of Si-CH3 groups. The DEMS based low-k film annealed up to 600 °C showed a leakage current of around 10−7A/cm2 at 9 MV/cm electric field.

Surfactants as an Additive to Wet Cleaning Solutions for Plasma Etch Residue Removal: Compatibility to a Porous CVD-SiCOH Ultra Low-k Dielectric Material

With decreasing feature sizes and integration of porous low-k dielectrics within the interconnect system of integrated circuits, plasma etch residue removal becomes challenging. Plasma cleaning processes are known to degrade low-k material's properties and wet cleaning becomes a promising alternative. Using water based cleaning solutions turns out to be critical as they may not be able to wet low-energy residue surfaces or to penetrate into small features. Lowering the surface tension of the solutions will be essential and the application of surfactants is a promising approach. We investigated the static and dynamic surface tension of different surfactant solutions in DIW and their compatibility to a porous CVD-SiCOH low-k dielectric. The choice of the rinsing solution applied after surfactant treatment turned out to be essential for removing residual surfactant species. Optical, electrical and structural analysis showed that in contrast to DIW an IPA-rinse is able to remove remaining surfactant species.

Effect of Surfactant as Additive in Wet Clean Solutions on Properties of Low-k Materials

The effect of surfactant in a cleaning chemical solution on two types of porous low dielectric constant (low-k) materials was investigated. For the microporous film (mean pore diameter ≤2 nm), the material properties are not affected by the presence of surfactant, polyoxyethylene octyl phenyl ether. On the contrary, for mesoporous material where the mean pore size is in the order of 3 nm, a substantial change in optical properties of the film was recorded. Spectroscopic ellipsometry, ellipsometric porosimetry, Fourier-transform infrared spectroscopy, and X-ray photoelectron spectroscopy data point to the incorporation of surfactant molecules into the bulk. An alternative way to reduce the surface tension of the solution without compromising the initial properties of low-k consists of using isopropyl alcohol as an additive. The material properties remained unchanged after wet treatment. The results also indicate that the properties of porous film, which had been contaminated/degraded by the presence of the surfactant inside of the pores, can be recovered by using an alcohol-containing aqueous solution or pure alcohol such as isopropyl alcohol.

Effects of CMP Process Conditions on Defect Generation in Low-k Materials: An Atomic Force Microscopy Study

The effects of chemical mechanical planarization (CMP) process parameters and consumables on the polish rate and defects generated in various low-k materials with k values ranging from 2.2 to 3.0 were studied in detail. The process consumables and conditions evaluated include slurry material (alumina and silica), pad type (soft and hard), polish pressure, and polish time. Atomic force microscopy (AFM) images and roughness numbers were used to evaluate the post-CMP defect generation under various process conditions and revealed nano/microscratches, pits, voids, and film delamination. For a given material, the removal rate increased with increasing pressure. The dependence of defects on pressure appeared highly driven by the slurry material, pad type, and low-k material properties. Defects increased with increasing pad hardness and decreasing k values. The increasing defects with decreasing k value can be attributed to the lower elastic modulus observed with low-k materials. Removal rates exhibited both a decrease and an increase in conjunction with polish time, depending on the type of low-k material used. AFM analysis showed an improvement in global surface roughness with increasing polish time; however, an increase in localized defects such as pits was also observed. Fourier transform infrared and X-ray photoelectron spectroscopy analyses showed no change in film chemistry under the conditions studied here. © 2004 The Electrochemical Society. All rights reserved.

Effect of Dielectric Materials on Stress-Induced Damage Modes in Damascene Cu Lines

ABSTRACTVarious low-k materials are being pursued as dielectric materials for future interconnects. However, poor thermo-mechanical properties of low-k materials cause tremendous reliability concerns, thus the proper materials for integration with Cu are not suggested yet. In this study, the line width and spacing dependence of damascene Cu lines embedded by TEOS and low-k materials (CORAL) was analyzed using x-ray diffraction. Generally, the hydrostatic stress of Cu/TEOS was greater than that of Cu/CORAL, while the opposite for von-Mises stress. Using a three-dimensional finite analysis (FEA), the effect of low-k materials on the stress and its distribution in via-line structures of dual damascene Cu interconnects was studied. In the case of Cu/TEOS, the hydrostatic stress was concentrated at the via and on the top of the lines, where it was suspected that the void would nucleate. On the other hand, in the via-line structures integrated with organic low-k materials, large von-Mises stress was maintained in the via. Therefore, the deformation of via, rather than voiding, may be the main failure mode in the interconnects with low-k materials.