Proper Extraction Technique Research Articles

Sentiment Analysis and Sarcasm Detection using Deep Multi-Task Learning.

Social media platforms such as Twitter and Facebook have become popular channels for people to record and express their feelings, opinions, and feedback in the last decades. With proper extraction techniques such as sentiment analysis, this information is useful in many aspects, including product marketing, behavior analysis, and pandemic management. Sentiment analysis is a technique to analyze people's thoughts, feelings and emotions, and to categorize them into positive, negative, or neutral. There are many ways for someone to express their feelings and emotions. These sentiments are sometimes accompanied by sarcasm, especially when conveying intense emotion. Sarcasm is defined as a positive sentence with underlying negative intention. Most of the current research work treats them as two distinct tasks. To date, most sentiment and sarcasm classification approaches have been treated primarily and standalone as a text categorization problem. In recent years, research work using deep learning algorithms have significantly improved performance for these standalone classifiers. One of the major issues faced by these approaches is that they could not correctly classify sarcastic sentences as negative. With this in mind, we claim that knowing how to spot sarcasm will help sentiment classification and vice versa. Our work has shown that these two tasks are correlated. This paper proposes a multi-task learning-based framework utilizing a deep neural network to model this correlation to improve sentiment analysis's overall performance. The proposed method outperforms the existing methods by a margin of 3%, with an F1-score of 94%.

Charge Carrier Mobility and Series Resistance Extraction in 2D Field‐Effect Transistors: Toward the Universal Technique

Abstract2D semiconductor field‐effect transistors (2D FETs) have emerged as a promising candidate for beyond‐silicon electronics applications. However, its device performance has often been limited by the metal‐2D semiconductor contact, and the non‐negligible contact resistance (RSD) not only deteriorates the on‐state current but also hinders the direct characterization of the intrinsic properties of 2D semiconductors (e.g., intrinsic charge carrier mobility, μint). Therefore, a proper extraction technique that can independently characterize the metal‐2D semiconductor contact behavior and the intrinsic properties of a 2D semiconducting layer is highly desired. In this study, a universal yet simple method is developed to accurately extract the critical parameters in 2D FETs, including characteristic temperature (To), threshold voltage (VT), RSD, and μint. The practicability of this method is extensively explored by characterizing the temperature‐dependent carrier transport behavior and the strain‐induced band structure modification in 2D semiconductors. Technology computer aided design simulation is subsequently employed to verify the precision of RSD extraction. Furthermore, the universality of the proposed method is validated by successfully implementing the extraction to various 2D semiconductors, including black phosphorus, indium selenide, molybdenum disulfide, rhenium disulfide, and tungsten disulfide with top‐ and bottom‐gated configurations.

DC Characterization of Different Advanced MOSFET Architectures

A review of recent results concerning the DC characterization of FD- and Double Gate SOI MOSFET’s and FinFETs in modern CMOS technologies is given. By proper extraction techniques, distinction between the different interaction mechanisms is done. Parameter extraction conducted at room and low temperature clearly indicates that the mobility is directly impacted by shrinking the gate length in sub 100nm architectures.

DC and low frequency noise characterization of FinFET devices

A detailed DC and LF noise characterization of FinFETs is carried out. Parameter extraction conducted at room and low temperature clearly indicates that the mobility is degraded at small gate length in sub 100 nm FinFETs, as was already found for GAA, FD-SOI and DG-MOS devices. By proper extraction technique, sidewall and top conductions are analyzed, showing that sidewall mobility is about 25–30% degraded as compared to the top surface conduction, likely resulting from Fin patterning-induced defects and/or crystal orientation difference. Trap density in high- k/metal gate stack is found much larger than in pure SiO 2 MOSFETs but with no further degradation at small Fin widths.