The heterogeneous integration of multiple ICs in a single package along with high performance/bandwidth memory is critical for many high performance computing applications. Such designs result in complex connectivity with many hundreds of thousands of connections after everything has been heterogeneously integrated and packaged. Such designs make it extremely challenging to verify the correctness of the connections. The traditional way to verify the connections requires a lot of manpower and time and is either not exhaustive or too late in the process as its typically done after implementation is complete. This paper will introduce a new way to functionally verify the packaging connectivity using formal verification that can exhaustively verify all interconnections between the IC blocks. The flow is automatic for all steps from creating connectivity spec to verify packaging output connectivity. The automatic parallel algorithms on compute grid can verify huge numbers of connections in minutes even seconds. The script for the flow is simple and only takes a few minutes to setup. Once the script is ready, it can be reused for different packaging projects.
Read full abstract