Program Worst Case Execution Time Research Articles

WCET-Aware Control Flow Checking With Super-Nodes for Resource-Constrained Embedded Systems

Safety-critical embedded systems in application domains, such as aerospace, automotive, and industrial automation, must satisfy dual requirements of fault-tolerance and real-time predictability. Control flow checking is an effective technique for improving embedded systems’ reliability by online monitoring and checking of software control flow to detect runtime deviations from the control flow graph. However, inserting instrumentation code in every basic block incurs significant execution time overhead, which may cause the program to violate its timing constraints. In this paper, we propose to selectively instrument a subset of code regions that are larger than basic blocks, called super-nodes, in order to make the program partially resilient to control flow errors while keeping the program worst-case execution time (WCET) below a given upper bound. WCET analysis is invoked to estimate the program WCET and to identify the corresponding worst-case execution path (WCEP). An ILP formulation is used to judiciously select a subset of super-nodes on the WCEP for instrumentation, so that the best fault detection coverage is achieved without violating the given WCET upper bound. The optimization is repeated for each identified WCEP until the program WCET satisfies the WCET upper bound. Experimental results demonstrate significant improvements of fault detection coverage compared with related work.

소스코드와 실행코드의 상관관계 분석을 통한 최악실행시간 측정 방법

내장 소프트웨어는 실시간성 및 실행 환경으로부터의 독립성을 요구사항으로 갖는다. 실시간성 요구사항은 탑재된 태스크의 최악 실행 시간으로부터 영향을 받는다. 따라서 실시간성을 보장하기 위해서는 정적 분석 기반의 최악 실행 시간 분석 방법을 사용하여 프로그램의 최악 실행 시간을 파악하여야 한다. 그러나 기존의 최악 실행 시간 분석은 실행 환경으로부터 독립성을 고려하지 않는다. 이에 우리는 실행 환경으로부터 독립성을 제공하기 위해 소스코드로부터 실행 시간을 측정하는 방법을 제시한다. 이를 위해 실행 코드가 아닌 소스코드로부터 생성된 제어 흐름 그래프를 통해 실행 시간을 측정한다. 또한 소스코드로부터 생성된 제어 흐름 그래프에는 실행 시간 정보가 존재하지 않기 때문에, 이를 제공하기 위해 소스코드의 문장과 실행코드의 명령어와의 관계를 분석한다. 결과적으로 실행 시간 측정이 가능한 제어 흐름 그래프를 생성할 수 있다. 이를 통해 프로세서로부터 종속적인 부분을 매개변수화할 수 있기 때문에, 최악 실행 시간 분석 도구의 유연성을 향상시킬 수 있다. Embedded software has requirements such as real-time and environment independency. The real-time requirement is affected from worst-case execution time of loaded tasks. Therefore, to guarantee real-time requirement, we need to determine a program's worst-case execution time using static analysis approach. However, the existing methods for worst-case execution time analysis do not consider the environment independency. Thus, in this paper, in order to provide environment independency, we propose a method for measuring task's execution time from the source codes. The proposed method measures the execution time through the control flow graph created from the source codes instead of the executable codes. However, the control flow graph created from the source code does not have information about execution time. Therefore, in order to provide this information, the proposed method identifies the relationships between statements in the source code and instructions in the executable code. By parameterizing those parts that are dependent on processors based on the relationships, it is possible to enhance the flexibility of the tool that measures the worst-case execution time.

WCET-Aware Energy-Efficient Data Allocation on Scratchpad Memory for Real-Time Embedded Systems

Scratchpad memory (SPM) is a software-managed, small, on-chip form of memory. For real-time embedded systems, worst case execution time (WCET) is more important than average-case performance. We address the problem of allocating program data variables between main memory and SPM to minimize the energy consumption due to data variable accesses, while respecting a given upper bound on a program’s WCET. We present an optimal branch-and-bound algorithm; and an efficient heuristic algorithm. Our approach provides a flexible framework for the designer to perform tradeoff analysis between the program WCET and the energy consumption based on application requirements.

WCET-Aware Partial Control-Flow Checking for Resource-Constrained Real-Time Embedded Systems

Real-time embedded systems in diverse application domains, such as industrial control, automotive, and aerospace, are often safety-critical systems with stringent timing constraints that place strong demands on reliability and fault tolerance. Since fault-tolerance mechanisms inevitably add performance and/or resource overheads, it is important to guarantee a system's real-time constraints despite these overheads. Control-flow checking (CFC) is an effective technique for improving embedded systems' reliability and security by online monitoring and checking of software control flow to detect runtime deviations from the control-flow graph (CFG). Software-based CFC has high runtime overhead, and it is generally not applicable to resource-constrained embedded systems with stringent timing constraints. We present techniques for partial CFC (PCFC), which aims to achieve a tradeoff between runtime overhead, which is measured in terms of increases in worst case execution time (WCET), and fault-detection coverage by selectively instrumenting a subset of basic blocks. Experimental results indicate that PCFC significantly enables reductions of the program WCET compared to full CFC at the cost of reduced fault-detection ratio, thus providing a tunable fault-tolerance technique that can be adapted by the designer to suit the needs of different applications.

Static analysis of multi-core TDMA resource arbitration delays

In the development of hard real-time systems, knowledge of the Worst-Case Execution Time (WCET) is needed to guarantee the safety of a system. For single-core systems, static analyses have been developed which are able to derive guaranteed bounds on a program's WCET. Unfortunately, these analyses cannot directly be applied to multi-core scenarios, where the different cores may interfere with each other during the access to shared resources like for example shared buses or memories. For the arbitration of such resources, TDMA arbitration has been shown to exhibit favorable timing predictability properties. In this article, we review and extend a methodology for analyzing access delays for TDMA-arbitrated resources. Formal proofs of the correctness of these methods are given and a thorough experimental evaluation is carried out, where the presented techniques are compared to preexisting ones on an extensive set of real-world benchmarks for different classes of analyzed systems.

Clustered Worst-Case Execution-Time Calculation

Knowing the worst-case execution time (WCET) of a program is necessary when designing and verifying real-time systems. A correct WCET analysis method must take into account the possible program flow, such as loop iterations and function calls, as well as the timing effects of different hardware features, such as caches and pipelines. A critical part of WCET analysis is the calculation, which combines flow information and hardware timing information in order to calculate a program WCET estimate. The type of flow information which a calculation method can take into account highly determines the WCET estimate precision obtainable. Traditionally, we have had a choice between precise methods that perform global calculations with a risk of high computational complexity and local methods that are fast but cannot take into account all types of flow information. This paper presents an innovative hybrid method to handle complex flows with low computational complexity, but still generate safe and tight WCET estimates. The method uses flow information to find the smallest parts of a program that have to be handled as a unit to ensure precision. These units are used to calculate a program WCET estimate in a demand-driven bottom-up manner. The calculation method to use for a unit is not fixed, but could depend on the included flow and program characteristics.

Modeling Control Speculation for Timing Analysis

The schedulability analysis of real-time embedded systems requires worst case execution time (WCET) analysis for the individual tasks. Bounding WCET involves not only language-level program path analysis, but also modeling the performance impact of complex micro-architectural features present in modern processors. In this paper, we statically analyze the execution time of embedded software on processors with speculative execution. The speculation of conditional branch outcomes (branch prediction) significantly improves a program's execution time. Thus, accurate modeling of control speculation is important for calculating tight WCET estimates. We present a parameterized framework to model the different branch prediction schemes. We further consider the complex interaction between speculative execution and instruction cache performance, that is, the fact that speculatively executed blocks can generate additional cache hits/misses. We extend our modeling to capture this effect of branch prediction on cache performance. Starting with the control flow graph of a program, our technique uses integer linear programming to estimate the program's WCET. The accuracy of our method is demonstrated by tight estimates obtained on realistic benchmarks.

Pipelined processors and worst case execution times

The calculation of worst case execution time (WCET) is a fundamental requirement of almost all scheduling approaches for hard real-time systems. Due to their unpredictability, hardware enhancements such as cache and pipelining are often ignored in attempts to find WCET of programs. This results in estimations that are excessively pessimistic. In this article a simple instruction pipeline is modeled so that more accurate estimations are obtained. The model presented can be used with any schedulability analysis that allows sections of nonpreemptable code to be included. Our results indicate the WCET overestimates at basic block level can be reduced from over 20% to less than 2%, and that the overestimates for typical structured real-time programs can be reduced by 17%–40%.