Programmable Processor Research Articles

Model-Independent Learning of Quantum Phases of Matter with Quantum Convolutional Neural Networks.

Quantum convolutional neural networks (QCNNs) have been introduced as classifiers for gapped quantum phases of matter. Here, we propose a model-independent protocol for training QCNNs to discover order parameters that are unchanged under phase-preserving perturbations. We initiate the training sequence with the fixed-point wave functions of the quantum phase and add translation-invariant noise that respects the symmetries of the system to mask the fixed-point structure on short length scales. We illustrate this approach by training the QCNN on phases protected by time-reversal symmetry in one dimension, and test it on several time-reversal symmetric models exhibiting trivial, symmetry-breaking, and symmetry-protected topological order. The QCNN discovers a set of order parameters that identifies all three phases and accurately predicts the location of the phase boundary. The proposed protocol paves the way toward hardware-efficient training of quantum phase classifiers on a programmable quantum processor.

Scalable and ultralow power silicon photonic two-dimensional phased array

Photonic integrated circuit based optical phased arrays (PIC-OPAs) are emerging as promising programmable processors and spatial light modulators, combining the best of planar and free-space optics. Their implementation on silicon photonic platforms has been especially fruitful. Despite much progress in this field, demonstrating steerable two-dimensional (2D) OPAs that are scalable to a large number of array elements and operate with a single wavelength has proven a challenge. In addition, the phase shifters used in the array for programming the far-field beam are either power hungry or have a large footprint, preventing the implementation of large scale 2D arrays. Here, we demonstrate a two-dimensional silicon photonic phased array with high-speed (∼330 kHz) and ultralow power microresonator phase-shifters with a compact radius (∼3 µm) and 2π phase shift ability. Each phase-shifter consumes an average of ∼250 µW of static power for resonance alignment and ∼50 µW of power for far-field beamforming, a more than one order of magnitude improvement compared to prior OPA works based on waveguide-based thermo-optic phase shifters. Such PIC-OPA devices can enable a new generation of compact and scalable low power processors and sensors.

Observation of critical phase transition in a generalized Aubry-André-Harper model with superconducting circuits

Quantum simulation enables study of many-body systems in non-equilibrium by mapping to a controllable quantum system, providing a powerful tool for computational intractable problems. Here, using a programmable quantum processor with a chain of 10 superconducting qubits interacted through tunable couplers, we simulate the one-dimensional generalized Aubry-André-Harper model for three different phases, i.e., extended, localized and critical phases. The properties of phase transitions and many-body dynamics are studied in the presence of quasi-periodic modulations for both off-diagonal hopping coefficients and on-site potentials of the model controlled respectively by adjusting strength of couplings and qubit frequencies. We observe the spin transport for initial single- and multi-excitation states in different phases, and characterize phase transitions by experimentally measuring dynamics of participation entropies. Our experimental results demonstrate that the recently developed tunable coupling architecture of superconducting processor extends greatly the simulation realms for a wide variety of Hamiltonians, and can be used to study various quantum and topological phenomena.

Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters

High performance and energy efficiency are critical requirements for Internet of Things (IoT) end-nodes. Exploiting tightly coupled clusters of programmable processors (CMPs) has recently emerged as a suitable solution to address this challenge. One of the main bottlenecks limiting the performance and energy efficiency of these systems is the instruction cache architecture due to its criticality in terms of timing (i.e., maximum operating frequency), bandwidth, and power. We propose a hierarchical instruction cache tailored to ultralow-power (ULP) tightly coupled processor clusters where a relatively large cache (L1.5) is shared by L1 private (PR) caches through a two-cycle latency interconnect. To address the performance loss caused by the L1 capacity misses, we introduce a next-line prefetcher with cache probe filtering (CPF) from L1 to L1.5. We optimize the core instruction fetch (IF) stage by removing the critical core-to-L1 combinational path. We present a detailed comparison of instruction cache architectures’ performance and energy efficiency for parallel ULP (PULP) clusters. Focusing on the implementation, our two-level instruction cache provides better scalability than existing shared caches, delivering up to 20% higher operating frequency. On average, the proposed two-level cache improves maximum performance by up to 17% compared to the state-of-the-art while delivering similar energy efficiency for most relevant applications.

Realizing symmetry-protected topological phases in a spin-1/2 chain with next-nearest-neighbor hopping on superconducting qubits

Quantum simulation on near-term quantum hardware is a topic of intense interest. The preparation of novel quantum states of matter provides a quantitative assessment of the capabilities of near-term digital quantum computers to implement circuits with structure of relevance to quantum simulation. Here, we conduct a benchmark study by realizing symmetry-protected topological (SPT) phases of a spin-1/2 Hamiltonian with next-nearest-neighbor hopping on up to 11 qubits on a programmable superconducting quantum processor using adiabatic state preparation. Using recompilation techniques to reduce the gate count to around 50 two-qubit gates, we observe clear signatures of the two distinct SPT phases, such as excitations localized to specific edges and finite string-order parameters. We identify a parasitic phase associated with the two-qubit gate as the dominant imperfection that limits the depth of the circuits, indicating a research topic of interest for future hardware development.

A scheduling framework for performing resource slicing with guarantees in 6G RIS-enabled smart radio environments

Smart Radio Environments (SRE) transform the wireless propagation phenomenon in a programmable process. Leveraging multiple Reconfigurable Intelligent Surfaces (RIS), the wireless waves emitted by a device can be almost freely routed and manipulated, reaching their end destination via improbable paths, with minimized fading and path losses. This work begins with the observation that each such wireless communication customization occupies a certain number of RIS units, e.g., to form a wireless path with consecutive customized reflections. Therefore, SREs can be modeled as a resource of constrained capacity, which needs to be sliced among interested clients. This work provides a foundational model of SRE-as-a-resource, defining Service Level Agreements (SLAs) and Service Level Objectives (SLOs) for the SRE client requests. Employing this model, we study a class of negative drift dynamic weighted round robin policies, that is able to guarantee specific SRE resource shares to competing user requests. We provide a general mathematical framework where the class of policies map ping user requests to resources does not require statistical knowledge regarding the arrival distribution or the duration of each user communication. We study the meaning of work conserving and non-work conserving modes of SRE operation, and also study the convergence properties of our scheduling framework for both cases. Finally, we perform the feasibility space analysis for our framework and we validate our analysis through extensive simulations.

An Overview of Telepractice Applications for Comprehensive Cochlear Implant Service Delivery

Purpose:Numerous follow-up appointments are required to program a cochlear implant (CI) sound processor and monitor the patient's progress over time, particularly within the first year of implantation. This, coupled with the specialty nature of CI service delivery and sparsely located clinics, can pose burdens on recipients' time and access to necessary resources for consistent follow-up. Advances in the application of telepractice for CI service delivery have evolved and expanded over recent years, with further utilization spurred by the COVID-19 pandemic that emerged in late 2019. This review article provides a summary of telepractice applications for adult and pediatric CI processor programming, impedance, and electrically evoked compound action potential testing, speech-perception testing, evaluations of patient and clinician experiences, troubleshooting, and aural rehabilitation for CI recipients. Future directions and opportunities for further implementation of telepractice for CI service delivery are discussed.Conclusions:Studies to date suggest that telepractice can be reliably used for remote sound processor programming for both children and adults, impedance and evoked compound action potential measures, speech-perception testing in adult CI users, and self-monitoring. However, further technological advancements are needed to make remote speech-perception testing more easily implemented, and well-controlled studies are needed to better evaluate the efficacies of aural rehabilitation through teletherapy, particularly for children.

Web-Based Information System for Listing Goods at the Semoga Jaya Store

Manual processing at the Semoga Jaya Store troubles the owner. This issue necessitates an information system that the business owner and customers can access immediately, at any time, and from any location. The system must offer precise, fast, and accurate information on the available stock. Hence, this study created a web-based information system designed with the Hypertext Processor (PHP) programming language and the MySQL database. The system could ease the store’s financial data management, offer information on its stock, and facilitate customers to discover information on the goods. This research involved needs analysis, system design, implementation, and testing. Functional testing was conducted on this stock list information system, revealing that it could facilitate data processing and provide information effectively and efficiently.

Low-loss chip-scale programmable silicon photonic processor

Chip-scale programmable optical signal processors are often used to flexibly manipulate the optical signals for satisfying the demands in various applications, such as lidar, radar, and artificial intelligence. Silicon photonics has unique advantages of ultra-high integration density as well as CMOS compatibility, and thus makes it possible to develop large-scale programmable optical signal processors. The challenge is the high silicon waveguides propagation losses and the high calibration complexity for all tuning elements due to the random phase errors. In this paper, we propose and demonstrate a programmable silicon photonic processor for the first time by introducing low-loss multimode photonic waveguide spirals and low-random-phase-error Mach-Zehnder switches. The present chip-scale programmable silicon photonic processor comprises a 1×4 variable power splitter based on cascaded Mach-Zehnder couplers (MZCs), four Ge/Si photodetectors, four channels of thermally-tunable optical delaylines. Each channel consists of a continuously-tuning phase shifter based on a waveguide spiral with a micro-heater and a digitally-tuning delayline realized with cascaded waveguide-spiral delaylines and MZSs for 5.68 ps time-delay step. Particularly, these waveguide spirals used here are designed to be as wide as 2 µm, enabling an ultralow propagation loss of 0.28 dB/cm. Meanwhile, these MZCs and MZSs are designed with 2-µm-wide arm waveguides, and thus the random phase errors in the MZC/MZS arms are negligible, in which case the calibration for these MZSs/MZCs becomes easy and furthermore the power consumption for compensating the phase errors can be reduced greatly. Finally, this programmable silicon photonic processor is demonstrated successfully to verify a number of distinctively different functionalities, including tunable time-delay, microwave photonic beamforming, arbitrary optical signal filtering, and arbitrary waveform generation.

Implementation of VLSI on Signal Processing-Based Digital Architecture Using AES Algorithm

Continuous improvements in very-large-scale integration (VLSI) technology and design software have significantly broadened the scope of digital signal processing (DSP) applications. The use of application-specific integrated circuits (ASICs) and programmable digital signal processors for many DSP applications have changed, even though new system implementations based on reconfigurable computing are becoming more complex. Adaptable platforms that combine hardware and software programmability efficiency are rapidly maturing with discrete wavelet transformation (DWT) and sophisticated computerized design techniques, which are much needed in today’s modern world. New research and commercial efforts to sustain power optimization, cost savings, and improved runtime effectiveness have been initiated as initial reconfigurable technologies have emerged. Hence, in this paper, it is proposed that the DWT method can be implemented on a field-programmable gate array in a digital architecture (FPGA-DA). We examined the effects of quantization on DWT performance in classification problems to demonstrate its reliability concerning fixed-point math implementations. The Advanced Encryption Standard (AES) algorithm for DWT learning used in this architecture is less responsive to resampling errors than the previously proposed solution in the literature using the artificial neural networks (ANN) method. By reducing hardware area by 57%, the proposed system has a higher throughput rate of 88.72%, reliability analysis of 95.5% compared to the other standard methods.

Improving the performance of quantum approximate optimization for preparing non-trivial quantum states without translational symmetry

The variational preparation of complex quantum states using the quantum approximate optimization algorithm (QAOA) is of fundamental interest, and becomes a promising application of quantum computers. Here, we systematically study the performance of QAOA for preparing ground states of target Hamiltonians near the critical points of their quantum phase transitions, and generating Greenberger–Horne–Zeilinger (GHZ) states. We reveal that the performance of QAOA is related to the translational invariance of the target Hamiltonian: without the translational symmetry, for instance due to the open boundary condition (OBC) or randomness in the system, the QAOA becomes less efficient. We then propose a generalized QAOA assisted by the parameterized resource Hamiltonian (PRH-QAOA), to achieve a better performance. In addition, based on the PRH-QAOA, we design a low-depth quantum circuit beyond one-dimensional geometry, to generate GHZ states with perfect fidelity. The experimental realization of the proposed scheme for generating GHZ states on Rydberg-dressed atoms is discussed. Our work paves the way for performing QAOA on programmable quantum processors without translational symmetry, especially for recently developed two-dimensional quantum processors with OBC.

Data Movement Accelerator Engines on a Prototype Power10 Processor

This article presents the design and implementation of active messaging engines (AMEs) on an IBM Power10 prototype chip. AMEs are tiny, simple, but fully programmable 64-bit processors, for offloading operations related to data movement. AMEs can offload the execution flow of the message passing interface and other messaging stacks from the host central processing unit, enabling truly asynchronous progress to overlap computation and communication. The AMEs are implemented as onboard OpenCAPI-compliant accelerators, leveraging existing OpenCAPI infrastructure. As realized in a 7-nm technology, each AME takes 0.034 mm2 of silicon area and 4.1 mW of power. AME performance is evaluated across several contiguous and noncontiguous memory copy scenarios. AMEs can perform up to the bandwidth limit of their access path to the main memory (32 GB/s) and incur a per-request overhead of about 600 ns. These results indicate that AMEs will confer advantages to general messaging libraries for processing, sending, and receiving on-node and off-node messages.

SISTEM INFORMASI RESERVASI KAMAR PADA HOTEL PALAPA TARUTUNG BERBASIS WEB

Today's computer is a human need in completing various activities, combined with the presence of data innovation that is increasingly taking part in the realm of work. Utilizing the right data innovation instruments, it will create fast and precise data as needed so that choices can be made quickly. The design of making a Room Reservation Information System at the Palapa Tarutung Hotel is an element that greatly influences the smooth operation of the hotel's operational tasks. Information that is less-accurate, less efficient, and less effective can be solved by implementing this system. In the preparation of this final project, the author's goal is to simplify and speed up room reservations. The author uses PHP (Hypertext Processor Programming) as a programming language, Xampp is used to run the web server, and MySQL is used for database management which is currently quite in demand.

A quantum annealing approach to solve max-cover problem

The Max-Cover is a NP-hard problem. Therefore, the heuristic approach is suitable to solve this problem for large instances. Quantum annealing is a heuristic quantum optimization algorithm that can be used to handle the Max-Cover problem. Recent developments in quantum technology allows creating programmable quantum processors to implement the quantum annealing technique. In this article, we apply the quantum annealing approach to solve the Max-Cover problem. The experimental results show that this approach gives better results than Simulated Annealing in terms of both solution quality and annealing time.

Chaotic Image Encryption Based on Boson Sampling

AbstractAs a fundamental form of information representation, image encryption is a significant research issue in the multimedia era. An image encryption scheme is proposed benefiting from chaotic random behavior characteristics of Boson sampling (BS) probability distribution, where the chaotic random number sequence is used to implement the encryption process including scrambling image pixels and altering the values of pixels. Further, a BS‐based image encryption prototype system is constructed on the programmable silicon photonic processor chip for BS with 5‐mode 2‐photon, which can encrypt 4 × 4 grayscale images. Besides, experiments for encrypting 256 × 256 gray‐scale images with 20‐mode 8‐photon BS are simulated on the StrawberryFields photonic quantum software platform. Numerical analyses demonstrate the proposed scheme has good effectiveness in terms of randomness test, information entropy, histogram, correlation, key space, key sensitivity, and anti‐attack, offering gains in many cryptographic applications. The BS‐based image encryption prototype system extends the application of BS to solve practical problems in addition to proving quantum advantages.

Parallel Implementations of ARIA on ARM Processors and Graphics Processing Unit

The ARIA block cipher algorithm is Korean standard, IETF standard (RFC 5794), and part of the TLS/SSL protocol. In this paper, we present the parallel implementation of ARIA block cipher on ARMv8 processors and GPU. The ARMv8 processor is the latest 64-bit ARM architecture and supports ASIMD for parallel implementations. With this feature, 4 and 16 parallel encryption blocks are implemented to optimize the substitution layer of ARIA block cipher using four different Sboxes. Compared to previous works, the performance was improved by 2.76× and 8.73× at 4-plaintext and 16-plaintext cases, respectively. We also present optimal implementation on GPU architectures. GPUs are highly parallel programmable processors featuring maximum arithmetic and memory bandwidth. Optimal settings of ARIA block cipher implementation on GPU were analyzed using the Nsight Compute profiler provided by Nvidia. We found that using shared memory reduces the execution timing when performing substitution operations with Sbox tables. When using many threads with shared memory instead of global memory, it improves performance by about 1.08∼1.43×. Additionally, techniques using table expansion to minimize bank conflicts have been found to be inefficient when tables cannot be copied by the size of the bank. We measured the performance of ARIA block ciphers implemented with various settings. This represents an optimized GPU implementation of the ARIA block cipher.

CMS ECAL upgrade for precision timing and energy measurements at the High Luminosity LHC

The unprecedented instantaneous luminosity provided by the High Luminosity upgrade of the LHC (HL-LHC) at CERN requires an upgrade of the Compact Muon Solenoid (CMS) electromagnetic calorimeter (ECAL). The barrel region of the CMS ECAL will be preserved but will be operated at a lower temperature and with a completely new readout and trigger electronics. A dual gain trans-impedance amplifier and an integrated circuit providing two 160 MHz analog to digital converter channels, gain selection, and data compression will be used in the new readout electronics. The trigger decision will be moved off-detector and performed by powerful and flexible field programmable gate array processors, allowing for sophisticated trigger algorithms to be applied. The upgraded ECAL will be capable of high-precision energy measurements throughout HL-LHC data taking and will greatly improve the time resolution for photons and electrons above 10 GeV.

Modular building blocks for mapping spiking neural networks onto a programmable neuromorphic processor

In the past few years, brain-inspired artificial intelligence (AI) system with energy-efficient neuromorphic computing has gathered lots of interests. However, how to build an efficient algorithm-to-hardware development tool for spiking neural networks (SNNs) remains a big challenge. In this paper, we present a novel design of neural controller which can flexibly generate the store-and-release signals in the designed SNNs. Further, we propose a mapping methodology with modular building blocks to deploy SNN models onto a many-core programmable neuromorphic processor. Experimental results show that the presented mapping method can be adaptive to various SNN layers of different sizes and quantization precisions. Besides, our demonstrated system on chip can achieve about 181 and 26 images per second runtime inference speed on MNIST and CIFAR-10 dataset respectively and show comparable accuracies and significantly better power performance with their artificial neural network (ANN) counterparts running on traditional GPU.

Foundations of Programmable Process Structures for the unified modeling and simulation of agricultural and aquacultural systems

This research paper defines the theoretical foundations and computational implementation of a non-conventional modeling and simulation methodology, inspired by the needs of problem solving for biological, agricultural, aquacultural and environmental systems. The challenging practical problem is to develop a framework for automatic generation of causally right and balance-based, unified models that can also be applied for the effective coupling amongst the various (sophisticated field-specific, sensor data processing-based, upper level optimization-driven, etc.) models. The scientific problem addressed in this innovation is to develop Programmable Process Structures (PPS) by combining functional basis of systems theory, structural approach of net theory and computational principles of agent based modeling. PPS offers a novel framework for the automatic generation of easily extensible and connectible, unified models for the underlying complex systems. PPS models can be generated from one state and one transition meta-prototypes and from the transition oriented description of process structure. The models consist of unified state and transition elements. The local program containing prototype elements, derived also from the meta-prototypes, are responsible for the case-specific calculations. The integrity and consistency of PPS architecture are based on the meta-prototypes, prepared to distinguish between the conservation-laws-based measures and the signals. The simulation is based on data flows amongst the state and transition elements, as well as on the unification based data transfer between these elements and their calculating prototypes. This architecture and its AI language-based (Prolog) implementation support the integration of various field- and task-specific models, conveniently. The better understanding is helped by a simple example. The capabilities of the recently consolidated general methodology are discussed on the basis of some preliminary applications, focusing on the recently studied agricultural and aquacultural cases.

A Programmable SRv6 Processor for SFC

A reconfigurable match table (RMT) is a programmable pipeline architecture for packet processing. In order to enable the programmable data plane to support segment routing IPv6 (SRv6) and other network protocols, this paper extends the deparser based on RMT. The paper uses the extended deparser and two RMT pipelines to build a protocol-independent network slice programmable data plane model named as the programmable SRv6 processor. We design it primarily for segment identifier (SID) processing of SRv6. We have proved that it can support SRv6, multiple semantics for SIDs, micro segment ID, multi-protocol label switching, and a service function chain (SFC). This architecture has broad application prospects. Experimental results on an FPGA showed that the extended deparser could achieve 100 Gbps throughput for 512B packets with few resources.