Programmable Logic Design Research Articles

Development of a Signal Processing Software for Scintillation Detectors and Implementation on an FPGA for Fast Sensing

An open-source code RadSigPro 1.0 has been developed and used for fast processing of nanosecond-long pulses from scintillation detectors. This processing includes pulse height distribution (PHD), pulse shape discrimination (PSD), and time of flight (TOF). The code has been implemented onto the programmable logic design of a field programmable gate array (FPGA) design for on-the-fly processing of neutron and gamma-ray pulses. A weighted average of the percent difference of the results for RadSigPro 1.0 implemented on a CPU and a FPGA logic design is calculated. This shows a 0% difference for the PHD data sets, a 0.458% and 0.344% difference for the designated gamma detector and neutron detector PSD data sets, respectively, and a 0% difference for the TOF data set. When the FPGA logic design is applied and simulated, it computed the total and tail pulse areas within 5 ns of the arrival of the final data point used for accumulation and also captured the pulse height value within 2 ns of the arrival of the pulse’s maximum data point.

A Concept of Visual Programming Tool for Learning VHDL

Due to the COVID-19 pandemic, distance education starts playing a crucial role in higher education and the need for development of educational tools, helping the students learn better at home cannot be ignored. Teaching programming languages online is a complicated task and when the course subject is programmable logic design through Hardware Description Languages (HDLs), online teaching becomes a complex challenge. In this paper is presented a concept of a training environment that uses the visual programing technique to help the students create VHDL models of various digital devices. The students construct VHDL models by combining simple visual objects while the environment is providing guidance in real time and is preventing a wrong match of VHDL operators and signals. The strategy for building a model of a compex digital circuit by moving and connecting visual objects will help the students with visual kinaesthetic learning style to internalize the concept and the structure of the VHDL model. The training environment will benefit mostly the students, learning in distance mode, but it is also useful for face-to-face students, who find it difficult to assimilate the specifics of VHDL modelling.

A Project-based Approach to FPGA-aided Teaching of Digital Systems

This article shares experience and lessons learned in teaching course on programmable logic design at Universitas Muhammadiyah Surakarta, Indonesia. This course is part of bachelor of engineering (electrical) degree program. Project-based approach is chosen to strengthen these students' understanding and practical skills. Each year's project involves challenges for the students to solve by implementing digital system on an FPGA design board. Here, background and curriculum context of the course will be presented. The projects and their challenges will be discussed. Finally, lessons learned and future improvement on the student projects will be discussed.

Research on the Design and Manufacture of Steam Cleaning Machine Based on PLC

In this paper, the programmable logic controller (PLC) produced the steam cleaning machine controller based on PLC and foundation design, and steam cleaning device controlled the process of the realization .The programmable logic controller PLC programming and logic design, system realizes according to different artifact types, complete cleaning, blowing, drying the corresponding action. This system after careful design, manufacturing and detailed inspection, and after the running test, the experimental results shows that: as long as the proper maintenance and proper use of equipment, the project can improve the efficiency to a great extent.

Programmable logic design of a compact Genetic Algorithm for phasor estimation in real-time

The main objective of this work is to present an efficient method for phasor estimation based on a compact Genetic Algorithm (cGA) implemented in Field Programmable Gate Array (FPGA). To validate the proposed method, an Electrical Power System (EPS) simulated by the Alternative Transients Program (ATP) provides data to be used by the cGA. This data is as close as possible to the actual data provided by the EPS. Real life situations such as islanding, sudden load increase and permanent faults were considered. The implementation aims to take advantage of the inherent parallelism in Genetic Algorithms in a compact and optimized way, making them an attractive option for practical applications in real-time estimations concerning Phasor Measurement Units (PMUs).

A Project-Based Learning Approach to Programmable Logic Design and Computer Architecture

This paper describes a course in programmable logic design and computer architecture as it is taught at the University of Newcastle, Australia. The course is designed around a major design project and has two supplemental assessment tasks that are also described. The context of the Computer Engineering degree program within which the course is taught is presented, and some student outcomes are discussed.

Teaching Discrete and Programmable Logic Design Techniques Using a Single Laboratory Board

Programmable logic devices (PLDs) are used at many universities in introductory digital logic laboratories, where kits containing a single high-capacity PLD replace “standard” sets containing breadboards, wires, and small- or medium-scale integration (SSI/MSI) chips. From the pedagogical point of view, two problems arise in these laboratories. First, students have some difficulties in understanding the link between discrete and programmable design techniques. Second, using only a single PLD, students are not automatically forced to learn modular design skills, which is one of the required learning outcomes in electrical engineering (EE) curricula. To overcome these problems, an innovative laboratory is proposed in this paper. Each training board contains four complex PLDs (CPLDs) and peripherals. In the initial sessions, students implement designs in which CPLDs are programmed as standard SSI/MSI chips and interconnected to construct the target circuit. Then, an active learning technique is used: Students form groups of any size and can set themselves more complex problems and choose their design approach. The proposed laboratory was set up at the Technical University of Lodz, Lodz, Poland, and the first classes were given in the 2008–2009 academic year. The instructors' insights and design reports and feedback from students were gathered and analyzed. The results showed the effectiveness of the novel approach. Students were deeply involved in solving self-imposed problems. They learned “engineering imagination,” modular design, and teamwork skills. Some groups went far beyond the requirements set by the instructor. However, an additional conclusion is that the “standard” approach should not be completely eliminated.

Professional Courses for Computer Engineering Education

A sequence of professional courses of study in Computer Engineering at the authors' university was initiated. These included Digital Fundamentals, Programmable Logic Design, Computer Hardware and Digital Systems Design. This paper presents a study on how the problem based learning has been used for these courses. It also describes how CDIO (Conceive, Design, Implement, Operate) concepts have been applied with an overview of all the hardware resources necessary to support the degree.

On Teaching Hardware/Software Co-design using FPGA

At Ruse University in the Faculty of Electrical Engineering, Electronics and Automation the students are offered several introductory courses that focus on microcontroller-based systems, embedded programming and Programmable Logic Design. In the process of design, configuration, and programming of microprocessors it is hard for the students to optimize the division of functions between hardware and software. One of the reasons is the growing number of advanced programming techniques and design principles, as well as sophisticated Integrated Development Environments. The courses have a fixed number of hours and the teacher cannot extend the content of the lectures and the labs. In order to improve the students’ knowledge and skills in the process of embedded systems design, the Hardware/Software Co-design is used in the teaching process. The paper considers one example of implementation of this approach in the design of a traffic light controller. The project is based on the Intellectual Property Core of PicoBlaze microcontroller, embedded within Xilinx Field Programmable Gate Array Families. For the project development Evaluation Board Spartan 3E including XC3S500E FPGA device is used.

A personal digital assistant-based portable radiation spectrometer

A nuclear spectrometer based on a personal digital assistant (PDA) has been designed, built and tested. This portable radiation spectrometer, PDA SPECTROMETER, can be used for data acquisition and spectrum analysis in a field that requiring output of radiation dose rate and count rate as well as nuclide identification. A Complex Programmable Logic Design (CPLD) circuit block is built for data communication with PDA through RS-232 serial interfaces, backed up by a global positioning system (GPS) unit. The architecture and the data acquisition block are optimized to accommodate high data throughput.

TOOLS AND TECHNOLOGIES FOR DESIGNING CONTROL SYSTEMS USING PROGRAMMABLE LOGIC DEVICES

The paper presents modern programmable logic devices and design methodologies with appropriate tools reference. It briefly shows enhancements introduced in the architecture of FPGA and its influence on circuit capabilities. The paper presents also the design process from idea to functional implementation. It discusses algorithmic and functional approaches to design. Abstraction level and transaction mechanisms are shown as a method of hiding details without compromising design functionality. Finally tools for different design approaches and design environment requirements are presented.

FPGA implementation and experimental evaluation of a multizone network cache

Network routers rely on content addressable memories (CAMs) to accelerate the process of looking up the next hop of a packet. The input for this lookup is the destination address of the packet. This article describes our implementation and evaluation of a versatile prototype for a CAM. This prototype allows the empirical evaluation of the idea of caching lookup results in a multizone cache organized according to the length of the network prefix portion of the addresses. Implementing a cache in an FPGA efficiently required the design of a new cache replacement policy, the Bank Nth Chance policy. In this article we present results from a functional simulator that allows the comparison of this new policy with existing ones such as least recently used, first in, first out and Second Chance. With a complete and functional prototype in a Xilinx Virtex 2000E device, we also report frequency of operation and occupation of the device. We present programmable logic design techniques that enable the implementation of ternary logic CAM cells, the efficient implementation of the new policy reference fields, and the pipelining of lookups.

FPGA implementation and experimental evaluation of a multizone network cache

Network routers rely on content addressable memories (CAMs) to accelerate the process of looking up the next hop of a packet. The input for this lookup is the destination address of the packet. This article describes our implementation and evaluation of a versatile prototype for a CAM. This prototype allows the empirical evaluation of the idea of caching lookup results in a multizone cache organized according to the length of the network prefix portion of the addresses. Implementing a cache in an FPGA efficiently required the design of a new cache replacement policy, the Bank Nth Chance policy. In this article we present results from a functional simulator that allows the comparison of this new policy with existing ones such as least recently used, first in, first out and Second Chance. With a complete and functional prototype in a Xilinx Virtex 2000E device, we also report frequency of operation and occupation of the device. We present programmable logic design techniques that enable the implementation of ternary logic CAM cells, the efficient implementation of the new policy reference fields, and the pipelining of lookups.

Designing a Beamline Equipment Protection System Using a Programmable Logic Controller

As part of the Synchrotron Radiation Instrumentation Collaborative Access Team (SRI-CAT), a new beamline equipment protection system was designed, implemented and installed. The beamline equipment protection system is designed to assure the safe operation of bending magnet and insertion device beamline components, such as white-beam slits, user filters, shutters and stops, mirrors and monochromators. Design goals of the equipment protection system were to improve equipment safety performance, reduce nuisance trips and incorporate additional system functions with minimal cost. To meet the requirements of such a safety system, it was configured to use a programmable controller, remote block input/output (I/O), local interfaces and a serial communication link known as remote I/O (RIO). Aspects about the design requirements, functionality and constraints are presented, as well as specifics on programmable ladder logic design, hardware selection, testing and interfacing requirements.

VLSI design and implementation of a real-time image segmentation processor

Image segmentation is a crucial part of machine vision applications. In this paper a system to perform real-time segmentation of images is presented. It uses a real-time segmentation VLSI chip that is based on a gradient relaxation algorithm and is designed using the Path Programmable Logic design methodology developed at the University of Utah. The system design considerations, system specifications, and an input/output format for the chip are discussed. The actual design of the chip is given that uses pipeline methodology to achieve real-time performance with a compact VLSI layout. The implementation of the segmentation system is presented and the segmentation chip and the overall system are evaluated with regard to real-time performance and segmentation results.

Wave digital filter hardware structure

A large amount of literature has been published during the last decade on the design of digital filter structures with desirable attributes, such as low round off noise, simple coefficients or ease of implementation. In this paper, the hardware implementation of a structure based on a classical doubly-terminated distributed filter prototype is discussed. This structure has a prarticularly simple form as it is a cascade of identical 1st-order networks. The paper describes a programmable logic design centred on a high-speed bipolar LSI multiplier chip. It is shown that a complete 6th degree wave digital filter with analogue I/O can be implemented on a single S-100 printed-circuit board, and further that the filter can operate at a maximum sampling rate of around 150 kHs. The filter coefficients can be change in the controll program which is also stored in PROM.