Programmable Gain Amplifier Research Articles

A Frontend for Magnetoresistive Sensors With a 2.2-pA/√Hz Low-Noise Current Source

In this letter, we present an integrated readout chip for magnetoresistive (MR) sensors consisting of a readout chain that comprises a dc-coupled fully differential difference amplifier (FDDA) followed by a programmable gain amplifier (PGA), as well as a low-noise current biasing scheme for the MR sensor. The current bias scheme features a 10-bit digital-to-analog converter (DAC) to compensate for process variations of the MR sensing element as well as to calibrate for variations in the dc bias field of the sensor. The bias current source achieves a very low current noise floor of 2.2 pA/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sqrt {\mathrm {Hz}}$ </tex-math></inline-formula> for bias currents up to 1 mA. The readout chip is manufactured in 180-nm SOI CMOS and consumes a total power of 38 mW. The letter is an extended version of (Mohamed <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">et al.</i> , 2021) incorporating additional modeling details and measurement results.

A Miniaturized 256-Channel Neural Recording Interface With Area-Efficient Hybrid Integration of Flexible Probes and CMOS Integrated Circuits.

We report a miniaturized, minimally invasive high-density neural recording interface that occupies only a 1.53 mm2 footprint for hybrid integration of a flexible probe and a 256-channel integrated circuit chip. To achieve such a compact form factor, we developed a custom flip-chip bonding technique using anisotropic conductive film and analog circuit-under-pad in a tiny pitch of 75 μm. To enhance signal-to-noise ratios, we applied a reference-replica topology that can provide the matched input impedance for signal and reference paths in low-noise aimpliers (LNAs). The analog front-end (AFE) consists of LNAs, buffers, programmable gain amplifiers, 10b ADCs, a reference generator, a digital controller, and serial-peripheral interfaces (SPIs). The AFE consumes 51.92 μW from 1.2 V and 1.8 V supplies in an area of 0.0161 mm2 per channel, implemented in a 180 nm CMOS process. The AFE shows > 60 dB mid-band CMRR, 6.32 μVrms input-referred noise from 0.5 Hz to 10 kHz, and 48 MΩ input impedance at 1 kHz. The fabricated AFE chip was directly flip-chip bonded with a 256-channel flexible polyimide neural probe and assembled in a tiny head-stage PCB. Full functionalities of the fabricated 256-channel interface were validated in both in vitro and in vivo experiments, demonstrating the presented hybrid neural recording interface is suitable for various neuroscience studies in the quest of large scale, miniaturized recording systems.

A Low-Power Digital Capacitive MEMS Microphone Based on a Triple-Sampling Delta-Sigma ADC With Embedded Gain

A triple-sampling &#x0394;&#x03A3; ADC can replace the programmable gain amplifier commonly used in the readout circuit for a digital capacitive MEMS microphone. The input voltage can then be multiplied by subtracting a further half-period delayed differential input and using the feedback capacitor of the DAC as a sampling capacitor. This triple-sampling technique results in a readout circuit with sensitivity and noise performance comparable to recent designs, but with a reduced power requirement. A MEMS microphone incorporating this readout circuit, fabricated in a 0.18 &#x03BC;m CMOS process, had an area of 0.98 mm², achieved an A-weighted SNR of 62.1 dBA at 94 dBSPL with 520 &#x03BC;A current consumption, to which triple-sampling was shown to contribute 4.5 dBA.

A low power and ultra-high input impedance analog front end based on fully differential difference inverter-based amplifier for biomedical applications

In this paper, a low power and low noise analog front end (AFE) is designed for biosignal acquisition. The first stage is a low noise amplifier (LNA) that is designed by combining the fully differential difference amplifier (FDDA) structure with inverter-based to achieve the optimal power, noise, CMRR, and input impedance simultaneously. Also, to increase the output resistance of the LNA, and subsequently increase the gain without reducing the output voltage swing, the gain boosting technique has been used. To use this structure for biosignals, the second stage is designed as a programmable gain amplifier (PGA). This AFE is reconfigurable for electroencephalography (EEG), electrocardiogram (ECG), and surface electromyography (sEMG) biosignals with variable gain of 71 dB, 56 dB, and 44 dB and bandwidth of (0.9–100 Hz), (1–560 Hz) and (12 Hz–1.5 kHz), respectively. The AFE consumes only 303 nW at 0.8 V supply voltage and confers excellent input impedance of 250 GΩ and 5.2 GΩ when the chopper is “off” and “on” respectively. The chopper method has been used and the total integrated input-referred noise is obtained, 1.4μVrms. The proposed AFE is simulated in TSMC 65 nm CMOS technology and occupies an area of 0.16mm2.

A 77-dB Dynamic-Range Analog Front-End for Fine-Dust Detection Systems with Dual-Mode Ultra-Low Noise TIA.

This paper presents an analog front-end for fine-dust detection systems with a 77-dB-wide dynamic range and a dual-mode ultra-low noise TIA with 142-dBΩ towards the maximum gain. The required high sensitivity of the analog signal conditioning path dictates having a high sensitivity at the front-end while the Input-Referred Noise (IRN) is kept low. Therefore, a TIA with a high sensitivity to detected current bio-signals is provided by a photodiode module. The analog front end is formed by the TIA, a DC-Offset Cancellation (DCOC) circuit, a Single-to-Differential Amplifier (SDA), and two Programmable Gain Amplifiers (PGAs). Gain adjustment is implemented by a coarse-gain-step using selective loads with four different gain values and fine-gain steps by 42 dB dynamic range during 16 fine steps. The settling time of the TIA is compensated using a capacitive compensation which is applied for the last stage. An off-state circuitry is proposed to avoid any off-current leakage. This TIA is designed in a 0.18 µm standard CMOS technology. Post-layout simulations show a high gain operation with a 67 dB dynamic range, input-referred noise, less than 600 fA/√Hz in low frequencies, and less than 27 fA/√Hz at 20 kHz, a minimum detectable current signal of 4 pA, and a 2.71 mW power consumption. After measuring the full path of the analog signal conditioning path, the experimental results of the fabricated chip show a maximum gain of 142 dB for the TIA. The Single-to-Differential Amplifier delivers a differential waveform with a unity gain. The PGA1 and PGA2 show a maximum gain of 6.7 dB and 6.3 dB, respectively. The full-path analog front-end shows a wide dynamic range of up to 77 dB in the measurement results.

A programmable gain and bandwidth amplifier based on tunable UGBW rail-to-rail CMOS op-amps suitable for different bio-medical signal detection systems

This work presents a bio-medical amplifier with programmable Gain and Bandwidth. The bandwidth of the proposed amplifier is controlled by tuning the unity-gain bandwidth (UGBW) of a rail-to-rail CMOS operational amplifier. The amplifier gain is controlled by changing the input capacitors keeping the bandwidth unchanged. The proposed bio-medical amplifier capable to accommodate different signals with a bandwidth ranging from 50 Hz up to 10 kHz to detect different bio-potential signals: EEG, ECG, EMG, PCG, and Aps, using fixed and small load capacitance. The proposed bio-medical amplifier consists of two stages each one designed with Tera ohm CMOS pseudo-resistors used in the amplifier feedback. The lower cutoff frequency of the bio-medical amplifier is tuned using two biasing currents in the CMOS pseudo-resistors, while two biasing voltages in the CMOS op-amps tune the higher cutoff frequency. The gain of the proposed bio-medical amplifier is ranging from 44.3 dB to 65.1 dB. High stability of the CMOS based op-amps (phase margin ≥60°) over the whole Gain and Bandwidth ranges is achieved. The overall power consumption of the bio-medical amplifier is less than 3.28 μW at the maximum gain settings of 65 dB and a maximum bandwidth of 10 k Hz. The total harmonic distortion of the proposed amplifier less than 1.21% for an input amplitude of 1 mVpk-pk over the entire bandwidth. The Input referred noise spectral density is 426 nV/Hz @1 kHz for the maximum bandwidth settings. The proposed bio-medical amplifier achieves an IIP3 value of 19.44 dBm for the amplifier gain of 54.9 dB. The simulation results show that the proposed bio-medical amplifier is robust against the PVT variations. LT-spice simulations using the standard 90 nm CMOS technology under 1 V supply voltage are performed to validate the theoretical results of the proposed amplifier.

A Bio-IA With Fast Recovery and Constant Bandwidth for Wearable Bio-Sensors

This paper proposes a bio-signal instrumentation amplifier (Bio-IA) with fast recovery and constant bandwidth for wearable bio-sensors. To shorten the offset calibration time of the Bio-IA and reduce the loss of bio-signal in the calibration process, a digital-controlled DC servo loop (DCDSL) with fast recovery is designed, which achieves a larger offset calibration range and a faster calibration speed. The proposed programmable gain amplifier (PGA) with constant bandwidth uses dual-biased pseudo-resistor (PR) to stabilize the passband width under different gains, effectively preventing the loss of low-frequency signals. Besides, this paper analyzes the noise of the DCDSL and the noise of dual-biased PR for the first time. The presented Bio-IA was implemented in a 0.18- μm CMOS process, occupying a core area of 849 μm×451 μm. The measured results show that the Bio-IA can calibrate a DC offset of ±511 mV, and the response time is less than 70 ms when the offset polarity changes suddenly. When the gain of the Bio-IA varies from 26 to 40 dB, its passband width remains constant, and the high-pass and low-pass cut-off frequencies are 0.4 Hz and 200 Hz, respectively. The input-referred noise over the range of 0.1-200 Hz is 0.72 μVrms. The proposed Bio-IA consumes 5.5 μW from 1.2 V supply voltage.

A Pipeline-TDC-Based CMOS Temperature Sensor with a 48 fJ·K2 Resolution FoM

An energy-efficient temperature sensor is important for temperature monitoring in Biomedical Internet-of-things (BIoT) applications. This article presents a time-domain temperature sensor with a pipeline time-to-digital converter (TDC). A programmable-gain time amplifier (PGTA) with high linearity and wide linear range is proposed to improve the resolution of the sensor and to reduce the chip area. The conversion time of the sensor is reduced by the fast TDC that only needs ~26 ns/conversion, which means the sensor is suitable for BIoT applications that commonly use duty cycling mode. Fabricated in a 40 nm standard CMOS technology, the sensor consumes 7.6 μA at a 0.6 V supply and achieves a resolution of 90 mK and a sensitivity of 0.62%/°C in a 1.3 μs conversion time. This translates into a resolution figure-of-merit of 48 fJ·K2. The sensor achieves an inaccuracy of 0.39 °C from −20 °C to 80 °C after two-point calibration. Duty cycling the sensor results in an even lower average power: ~18.6 nW at 10 conversions/s.

Design of 0–15 GHz flat-bandwidth programmable gain amplifier based on transconductance switching technique

Gain flatness is an important technical indicator for ADC-Based SerDes in practical applications. Due to the serial interface's unknown channel characteristics, signal amplitudes at the SerDes receiver remain uncertain. Therefore, the I/O interface needs to cover a wide gain range to meet the system linearity and signal amplitude requirements. This research introduced an input-transistor switching technique for the programmable gain amplifier (PGA), which adjusts the gain by changing the input transistor's number and effective transconductance to avoid the gain-rising problem in the existing PGA structures at high frequency. The core circuit of this research adopts a inductorless structure that can save the die area. Simulation results have shown that under the TSMC CMOS 40 nm process, the use of source degeneration zero compensation technique can achieve 0–15 GHz bandwidth with +0.05 dB variation, −7.3-6.6 dB gain tuning range. The circuit voltage is 1.8V, and the power consumption is 8.208 mW.

A true random number generator that utilizes thermal noise in a programmable system‐on‐chip (PSoC)

SummaryThis study presents four designs for a true random number generator (TRNG) for Cypress programmable system‐on‐chip (SoC) (PSoC) devices, whose entropy source is the thermal noise of resistors. The first design includes a ΔΣ analog‐to‐digital converter (ADC) with two external resistors of 6 MΩ, where the resolution was set to 16 bits. The second, third, and fourth designs adopt the internal resistors of a programmable gain amplifier (PGA) as a noise source. The second design adopts a single‐stage PGA (gain 50) with a ΔΣ ADC, while the third design adopts a two‐stage PGA (gain 50 × 50) with a ΔΣ ADC. The fourth design adopts a trans‐impedance amplifier (TIA) with a ΔΣ ADC. All four designs have passed the National Institute of Standards and Technology (NIST) test suite.

Column amplification stages in CMOS image sensors based on incremental sigma-delta ADCs

This paper focuses on the assessment of using programmable gain amplifiers on fast image sensor devices targeting low-light noise performance, comparing the responses of three on-chip column gain amplifier structures. Subsequent conclusions are derived from the usage of column amplifiers for imagers, retrieved from the comparison work. Based on the conducted study and the fabricated silicon device outputs, conclusive directions are pointed to determine the most optimal actions to adopt on future low-noise CMOS imagers. This work has revealed that the usage of amplification stages are essential for image sensors targeting low-noise, employing fast high-order incremental sigma-delta converters. Furthermore, the newest characterization results are also presented, done at a higher pixel supply voltage level. The measured performance improved from previous and early characterization, exhibiting 0.77% overall system non-linearity and featuring 2.91e-input-referred noise for the total readout chain noise at the same region of interest in the earlier work. Increasing the pixel supply has led to superior overall sensor performance.

A 15.5x-gain 0.29-mm2 CMOS readout circuit for 1.5-Mpixel 60-fps CMOS image sensor

An analog signal processing (ASP) circuit used for CMOS image sensor (CIS) readout is presented. The proposed ASP mainly includes a two-stage programmable gain amplifier (PGA), a sample-and-hold amplifier (SHA) merged by a pipelined analog–digital converter (ADC), and a digital-analog converter (DAC). Compared with conventional readout architecture, the proposed can provide finer gain, level shifting as well as offset calibrating function. A 1.5-Mpixel 60-fps CIS with the ASP is fabricated in a 0.13 μm 1P4M CMOS mixed signal process. The experiment results indicate the sensor can normally capture images without missing code. Moreover, the measured maximum gain error of the PGA is 1.6%, and the power dissipation is 16.5 mW for single ASP.

14‐Bit Fully Differential SAR ADC with PGA Used in Readout Circuit of CMOS Image Sensor

This paper proposes a 14‐bit fully differential Successive Approximation Register (SAR) Analog‐to‐Digital Converter (ADC) with a programmable gain amplifier (PGA) used in the readout circuit of CMOS image sensor (CIS). SAR ADC adopts two‐step scaled‐reference voltages to realize 14‐bit conversion, aimed at reducing the scale of capacitor array and avoiding using calibration to mitigate the impact of offset and mismatch. However, the reference voltage self‐calibration algorithm is applied on the design to guarantee the precision of reference voltages, which affects the results of conversion. The three‐way PGA provides three types of gains: 3x, 4x, and 6x, and samples at the same time to get three columns of pixel signal and increase the system speed. The pixel array of the mentioned CIS is 1026 × 1024, and the pixel pitch is 12.5 μm × 12.5 μm. The prototype chip is fabricated in the 180 nm CMOS process, and both digital and analog voltages are 3.3 V. The total area of the chip is 6.25 × 18.38 mm2. At 150 kS/s sampling rate, the SNR of SAR ADC is 71.72 dB and the SFDR is 82.91 dB. What is more, the single SAR ADC consumes 477.2 uW with the 4.8 VPP differential input signal and the total power consumption of the CIS is about 613 mW.

A 760-nW, 180-nm CMOS Fully Analog Voice Activity Detection System for Domestic Environment

This article presents a fully analog, signal-to-noise-ratio-based voice-activity detection (VAD) circuit. The circuit is based on an energy-efficient analog implementation with continuous-time nonlinear operation and fully passive switched-capacitor signal processing. The overall chain is composed of a programmable-gain amplifier, a squarer, an integrator, an SC-based signal averaging circuit, and a periodic threshold update circuit for adaptability. This implementation allows the minimization of both power consumption and chip area. The VAD circuit prototype has been fabricated in a 180-nm CMOS technology and occupies an area of 0.14 mm2. The device achieves 99.5% classification accuracy in a domestic environment in the presence of loud ambient noise, consuming 760 nW from a 1.2-V supply.

An ultra-low-power neural signal acquisition analog front-end IC

A four-channel, power-efficient, low-noise neural recording analog front-end (AFE) integrated circuit (IC) comprised of a low-noise amplifier (LNA), a programmable gain amplifier (PGA), and buffers is presented. The proposed AC-coupled capacitive-feedback LNA utilizes the inverter-stacking technique for the core operational transconductance amplifier which achieves four-time reduction in noise at minimal power consumption. The proposed PGA provides additional gain with tunable filtering function where the high-pass cut-off and low-pass cut-off frequencies can be controlled to acquire action potential and local field potential signals either simultaneously or separately. The overall AFE IC has a programmable gain range from 45 ​dB to 63 ​dB and achieves integrated input-referred noise of 3.16 μVRMS within the 10 ​kHz bandwidth, leading to a noise efficiency factor of 2.04 and power efficiency factor of 4.16. The AFE IC is implemented using 180 ​nm CMOS process and consumes 2.82 ​μW per channel powered from the 1-V supply voltage.

External temperature sensor assisted a new low power photoplethysmography readout system for accurate measurement of the bio-signs.

This study presents an external temperature sensor assisted a new low power, time-interleave, wide dynamic range, and low DC drift photoplethysmography (PPG) signal acquisition system to obtain the accurate measurement of various bio signs in real-time. The designed chip incorporates a 2-bit control programmable transimpedance amplifier (TIA), a high order filter, a 3:8 programmable gain amplifier (PGA) and 2 × 2 organic light-emitting diode (OLED) driver. Temperature sensor is used herein to compensate the adverse effect of low-skin-temperature on the PPG signal quality. The analog front-end circuit is implemented in the integrated chip with chip area of 2008 μm × 1377 μm and fabricated via TSMC T18 process. With the standard 1.8 V, the experimental result shows that the measured current sensing range is 20 nA–100 uA. The measured dynamic range of the designed readout circuit is 80 dB. The estimated signal to noise ratio is 60 dB@1 uA, and the measured input referred noise is 60.2 pA/Hz½. The total power consumption of the designed chip is 31.32 µW (readout) + 1.62 mW (OLED driver@100% duty cycle). The non-invasive PPG sensor is applied to the wrist artery of the 40 healthy subjects for sensing the pulsation of the blood vessel. The experimental results show that for every 1 °C decrease in mean ambient temperature tends to 0.06 beats/min, 0.125 mmHg and 0.063 mmHg increase in hear rate (HR), systolic (SBP) and diastolic (DBP), respectively. Similarly, for every 1 °C increase in mean ambient temperature tends to 0.13 beats/min, 0.601 mmHg and 0.121 mmHg increase in HR, SBP and DBP, respectively. The measured accuracy and standard error for the HR estimation are 96%, and − 0.022 ± 2.589 beats/minute, respectively. The oxygen stauration (SpO2) measurement results shows that the mean absolute percentage error is less than 5%. The resultant errors for the SBP and DBP measurement are − 0.318 ± 5.19 mmHg and − 0.5 ± 1.91 mmHg, respectively.Electronic supplementary materialThe online version of this article (10.1007/s00542-020-05106-y) contains supplementary material, which is available to authorized users.

An Active Concentric Electrode for Concurrent EEG Recording and Body-Coupled Communication (BCC) Data Transmission.

This paper presents a wearable active concentric electrode for concurrent EEG monitoring and Body-Coupled Communication (BCC) data transmission. A three-layer concentric electrode eliminates the usage of wires. A common mode averaging unit (CMAU) is proposed to cancel not only the continuous common-mode interference (CMI) but also the instantaneous CMI of up to 51Vpp. The localized potential matching technique removes the ground electrode. An open-loop programmable gain amplifier (OPPGA) with the pseudo-resistor-based RC-divider block is presented to save the silicon area. The presented work is the first reported so far to achieve the concurrent EEG signal recording and BCC-based data transmission. The proposed chip achieves 100dB CMRR and 110dB PSRR, occupies 0.044 mm2, and consumes 7.4μW with an input-referred noise density of 26nV/√Hz.

Ultrasensitive Magnetic Sensors Enabled by Heterogeneous Integration of Graphene Hall Elements and Silicon Processing Circuits.

Graphene Hall elements (GHEs) have been demonstrated to be promising magnetic field sensors with excellent sensitivity, linearity, temperature stability, and compatibility with complementary-metal-oxide-semiconductor (CMOS)-integrated circuits (ICs). However, the demonstrated GHEs have still not exhibited a comprehensive advantage in performance over commercial integrated Hall sensors which were implemented in integrated Hall element and CMOS processing ICs. In this work, we develop a technology for the three-dimensional (3D) heterogeneous integration of silicon-based CMOS ICs and GHEs, and the fabricated magnetic field sensors outperform commercial high-end integrated Hall sensors. Specifically, the integrated Hall sensors are implemented in a stacked integration on Si based on a chopper programmable-gain amplifier (CPGA), a chopper-stabilized second-order sigma-delta modulator (CSDM), and graphene-based Hall elements on monochips. GHEs with high sensitivity (up to 1000 A/VT) are fabricated with a compatible process on a smoothened silicon nitride passivation layer of silicon-based CMOS ICs, and the two device layers are connected by an interlayer. The heterogeneous integrated Hall ICs exhibit current and voltage magnetic sensitivities up to 64 000 A/VT and 6.12 V/VT, respectively, which are much higher than those in all other reported nanomaterial-based Hall sensors and even in high-end commercial Hall ICs. Furthermore, the 3D heterogeneous integration technology used here can be extended as a universal technology for integrating nanomaterial-based sensors and Si CMOS ICs.

Memristor and its Applications: A Comprehensive Review

The emergence of memristor offers new avenues to look at several potential applications ranging from non-volatile memories to neuromorphic system. A typical sign of the physical memristor device is Pinched Hysteresis Loop. In the aspect of accomplishing this loop with high accuracy, several memristor models have been evolved in the past. Moreover, various mathematical window functions have been developed from the researchers to throw more insight into the memristor model with the accordance of enhancing the degree of nonlinearity, resolving boundary effect and boundary lock. This review portrays a brief description of explored memristor models and window functions. With this, a comprehensive analysis is made to depict the advantages and disadvantages in a more explicit manner. Furthermore, this work exhibits the prevailing properties of memristor and the different types of switching mechanisms. Here, the future perspective of the memristive technology is also explored very well as the memristor has become an innovative candidate in the memory technology over the semiconductor. Memristor-based potential applications such as a fine resolution programmable gain amplifier, synapse, and logic gate are also explained briefly.

직류 오프셋 제거 회로를 가진 저 전력 프로그램 가능한 이득 증폭기 설계

In this paper, a low-power gain control amplifier with a direct current offset cancellation circuit is proposed in order to amplify analog signals. The proposed PGA (Programmable Gain Amplifier) is less sensitive to external influences due to the inclusion of active load on differential amplifiers. The PGA connects a direct current offset cancellation circuit, based on the Miller effect, to a differential amplifier stage to reduce area and compensate for distortion or lack of linearity. This circuit is also designed to be adjustable in eight steps, from 4 dB to 60 dB, using gain controls. The proposed PGA is designed using the TSMC 0.13 μm CMOS process, and was verified by simulation in ADS (Advanced Design System) tool. Compared to conventional research results, the proposed PGA achieved a gain error of less than 0.1 dB and a lower consumption of 0.16 mW.