Programmable Delay Line Research Articles

Design and application of a GaAs digital RF memory chip

The design and performance of a GaAs integrated memory/logic chip designed for digital RF memory (DRFM) applications is described. This chip, called a programmable delay-line element (PDLE), implements the basic DRFM storage and delay functions. The RAM-with-logic configuration combines a 4-kb static RAM with 750 logic gates, providing on a single chip the components for storage, address generation, demultiplexing, multiplexing, and control functions normally provided by a variety of separate chips. A distributed control organization, where the chip is configured to provide as outputs all the signals required as inputs to another identical chip, is used. Chips cascaded into strings implement the programmable delay lines required for DRFM systems. Problems associated with complex signal distribution networks are avoided since, within a string, signal distribution requires only local interconnections between adjacent chips. Correct operation of all functions was demonstrated in a four-chip string which provides a total memory capacity of 16 kb. The maximum sampling rate was 800 MHz, and power dissipation was approximately 2 W per chip. >

Prototype Binary Fiber Optic Delay Line

The operation and features of an electronically switched, programmable binary fiber optic delay line are discussed. The design, component selection, fabrication, testing, and evaluation of a prototype are presented. The prototype comprises seven delay stages, has a maximum delay of 5µs and a resolution of 39 ns, operates over the 0.5 to 1 GHz band with a dynamic range of 36 dB, and has a power consumption of 19 W.

A new high-performance programmable delay line IC

A novel implementation of a programmable digital delay line based on a shift register for video applications is presented. An optimized register developed to reduce the power dissipation of the register files is described. A compromise between the power dissipation and area of the circuit is used to obtain high performance. The chip features a 20-MHz operating frequency and 200-mW power dissipation. This chip has been designed with a 1.2- mu m CMOS technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The status of magnetostatic devices

Techniques under investigation to modify the dispersion and bandwidth of magnetostatic waves for device applications are Briefly reviewed. Four devices exhibiting useful characteristics are described in detail. These are a delay line with a delay against frequency variation which is linear within ± 5nS over a 1GHz bandwidth in X-band, a programmable 4-tap delay line which can generate and correlate Barker coded signals at 9GHz, a delay stabilized oscillator showing better frequency stability with temperature than YIG sphere oscillators and a signal to noise enhancer. This latter device is unique as it provides a low loss to coherent signals above a threshold power but increased losses to broadband noise or other signals below threshold.

Programmable CCD correlator

A programmable CCD tapped delay line, useful in radar and communications signal processors, is described. The 64-stage CCD, tapped at each stage, has been operated as a binary-weighted analog correlator, and as a bandpass filter. The CCD is a shallow, buried, n-channel device while the on-chip logic required for reference code input and storage is NMOS. Test results indicate near-theoretical peak-to-sidelobe ratio for 64-bit codes, good linearity, and high-speed operation (in excess of 15 MHz). Differential subtraction of summed signal currents on-chip has been demonstrated.

An improved programmable delay line

A programmable delay line has been developed that makes use of microstrip transmission line and temperature compensated ECL gates. This instrument delays standard NIM pulses and has settings of 0–64.5 ns. The output risetime is ⋍ 1 ns, independent of the delay setting. The delay stability at maximum delay is ⋍ 130 ppm/ °C, which is better than for RG-55 B/U coaxial cable. The minimum pulse width is less than 3 ns, and the difference in pulse width between the output and the input is less than 150 ps. Design tradeoffs and performance measurements are described.

Evaluation of new single crystal piezoelectric materials for surface acoustic-wave applications

Surface acoustic waves (SAW), or Rayleigh waves, bound to the surfaces of piezoelectric materials are becoming rapidly significant in electronic device applications, particularly as VHF-UHF frequency filters and versatile time-domain processors. The majority of available devices utilize either signle crystalline quartz or lithium niobate as the piezoelectric medium. This paper describes briefly the growth and critical evaluation of SAW impedance and propagation properties for certain new single crystal piezoelectric materials. Crystals discussed are Czochralski-grown bismuth germanium oxide, films of zinc oxide and aluminum nitride both epitaxially grown on single crystal sapphire, and flux-grown beryllium oxide. It is concluded that bismuth germanium oxide may prove an important cost-effective alternative to both quartz and lithium niobate, and that either zinc oxide or aluminum nitride is destined to prove invaluable in the realization of monolithic circuits such as programmable tapped delay lines, in which SAW will be interfaced with metal-oxide semiconductor (large scale integrated) technology, and active SAW elements employing functional integration.