Programmable Decoder Research Articles

Selective recognition of N4-methylcytosine in DNA by engineered transcription-activator-like effectors.

The epigenetic DNA nucleobases 5-methylcytosine (5mC) and N4-methylcytosine (4mC) coexist in bacterial genomes and have important functions in host defence and transcription regulation. To better understand the individual biological roles of both methylated nucleobases, analytical strategies for distinguishing unmodified cytosine (C) from 4mC and 5mC are required. Transcription-activator-like effectors (TALEs) are programmable DNA-binding repeat proteins, which can be re-engineered for the direct detection of epigenetic nucleobases in user-defined DNA sequences. We here report the natural, cytosine-binding TALE repeat to not strongly differentiate between 5mC and 4mC. To engineer repeats with selectivity in the context of C, 5mC and 4mC, we developed a homogeneous fluorescence assay and screened a library of size-reduced TALE repeats for binding to all three nucleobases. This provided insights into the requirements of size-reduced TALE repeats for 4mC binding and revealed a single mutant repeat as a selective binder of 4mC. Employment of a TALE with this repeat in affinity enrichment enabled the isolation of a user-defined DNA sequence containing a single 4mC but not C or 5mC from the background of a bacterial genome. Comparative enrichments with TALEs bearing this or the natural C-binding repeat provides an approach for the complete, programmable decoding of all cytosine nucleobases found in bacterial genomes.This article is part of a discussion meeting issue 'Frontiers in epigenetic chemical biology'.

Complete, Programmable Decoding of Oxidized 5-Methylcytosine Nucleobases in DNA by Chemoselective Blockage of Universal Transcription-Activator-Like Effector Repeats.

5-Methylcytosine (5mC) and its oxidized derivatives are regulatory elements of mammalian genomes involved in development and disease. These nucleobases do not selectively modulate Watson-Crick pairing, preventing their programmable targeting and analysis by traditional hybridization probes. Transcription-activator-like effectors (TALEs) can be engineered for use as programmable probes with epigenetic nucleobase selectivity. However, only partial selectivities for oxidized 5mC have been achieved so far, preventing unambiguous target binding. We overcome this limitation by destroying and re-inducing nucleobase selectivity in TALEs via protein engineering and chemoselective nucleobase blocking. We engineer cavities in TALE repeats and identify a cavity that accommodates all eight human DNA nucleobases. We then introduce substituents with varying size, flexibility, and branching degree at each oxidized 5mC. Depending on the nucleobase, substituents with distinct properties effectively block TALE-binding and induce full nucleobase selectivity in the universal repeat. Successful transfer to affinity enrichment in a human genome background indicates that this approach enables the fully selective detection of each oxidized 5mC in complex DNA by programmable probes.

Reliable Antifuse One-Time-Programmable Scheme With Charge Pump for Postpackage Repair of DRAM

A reliable antifuse (AF) one-time-programmable (OTP) cell and its sensing plus programming circuits for postpackage repair of dynamic random access memory (DRAM) are presented. The OTP cell was fabricated without any process modifications by utilizing destructive breakdown of thin gate oxide of nMOS capacitor as storage. The measurement results of OTP array fabricated by 0.13- $\mu $ m CMOS process show a tight read current distribution after programming. For pin compatibility with standard DRAM specifications, an internal charge pump is designed to provide high program voltage without any additional pin. Based on the AF cells, a programmable decoder is proposed to store the address of failed bit, decode the input address, and decide whether to access normal bit or redundant one of DRAM. The whole bit-repair scheme uses static latches as redundant cells. By avoiding the uses of address comparator and multiplexer, the proposed scheme shows less access penalty compared with prior scheme.

High-Throughput Trellis Processor for Multistandard FEC Decoding

Trellis codes, including Low-Density Parity-Check (LDPC), turbo, and convolutional code (CC), are widely adopted in advanced wireless standards to offer high-throughput forward error correction (FEC). Designing a multistandard FEC decoder is of great challenge. In this paper, a trellis application specified instruction-set processor (TASIP) is presented for multistandard trellis decoding. A unified forward-backward recursion kernel with an eight-state parallel trellis structure is proposed. Based on the kernel, a datapath for multialgorithm and a shared memory subsystem are introduced. The flexibility and the compatibility are guaranteed by a programmable decoding flow and the trellis decoding instruction set. Synthesis results show that the area consumption is 2.12 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (65 nm). TASIP provides trimode FEC decoding ability with the throughput of 533, 186, and 225 Mb/s for LDPC, turbo, and 64 states CC under the clock frequency of 200 MHz, which outperforms other trimode proposals both in area efficiency and recursion efficiency. TASIP provides high-throughput decoding for current standards, including 3rd Generation Partnership Project-Long Term Evolution, 802.16e, and 802.11n, with unified architecture and high compatibility.

Hardware/Software Co-reconfigurable Instruction Decoder for Adaptive Multi-core DSP Architectures

A programmable instruction decoder (PID) is introduced for designing adaptive multi-core DSP architectures by using a hardware/software co-reconfigurable approach without employing programmable devices. This PID permits DSP software developers for post-manufacturing modification of their DSP instruction sets to add their application-specific instructions whenever necessary. In addition, PID offers software developers an enhanced means to utilize the underlying DSP architectures by rescheduling implemented micro-operations for their tailored instructions in the DSP processors. Thus, emerging DSP applications can be swiftly and efficiently re-imported to PID-based DSP processors without re-fabrication of new DSP chips. In addition to instruction-level modification, an innovative instruction-packing procedure for PID is presented for further enhancement of the PID-based DSP systems. PID architecture was developed and implemented in VHDL. The PID-based DSP systems were also developed and evaluated to demonstrate various post-manufacturing adaptabilities in DSP processor systems. Various multi-core DSP architectures based on Texas Instruments' TMS320C55 DSP processor were used for evaluating performance and adaptability of this new programmable instruction decoder.

Reducing cache misses through programmable decoders

Level-one caches normally reside on a processor's critical path, which determines clock frequency. Therefore, fast access to level-one cache is important. Direct-mapped caches exhibit faster access time, but poor hit rates, compared with same sized set-associative caches because of nonuniform accesses to the cache sets. The nonuniform accesses generate more cache misses in some sets, while other sets are underutilized. We propose to increase the decoder length and, hence, reduce the accesses to heavily used sets without dynamically detecting the cache set usage information. We increase the access to the underutilized cache sets by incorporating a replacement policy into the cache design using programmable decoders. On average, the proposed techniques achieve as low a miss rate as a traditional 4-way cache on all 26 SPEC2K benchmarks for the instruction and data caches, respectively. This translates into an average IPC improvement of 21.5 and 42.4% for SPEC2K integer and floating-point benchmarks, respectively. The B-Cache consumes 10.5% more power per access, but exhibits a 12% total memory access-related energy savings as a result of the miss rate reductions, and, hence, the reduction to applications' execution time. Compared with previous techniques that aim at reducing the miss rate of direct-mapped caches, our technique requires only one cycle to access all cache hits and has the same access time of a direct-mapped cache.

A 1.9 Gb/s 358 mW 16–256 State Reconfigurable Viterbi Accelerator in 90 nm CMOS

A 16-256 state coarse-grain reconfigurable Viterbi accelerator fabricated in 1.3 Vt 90 nm dual-CMOS technology is described for 3.8 GHz operation, with 1.9 Gb/s data rate in 32-state mode. Radix-4 ripple-carry ACS circuits, reconfigurable path metric read/write control, and tree-bitline traceback memory circuits with programmable ring-buffer decoders enable 358 mW total power, measured at 1.3 V, 50degC, with performance scalable to 2.35 Gb/s at 1.7 V, 50degC.

Balanced Cache

Level one cache normally resides on a processor's critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared with same sized set-associative caches due to nonuniform accesses to the cache sets, which generate more conflict misses in some sets while other sets are underutilized. We propose a technique to reduce the miss rate of direct mapped caches through balancing the accesses to cache sets. We increase the decoder length and thus reduce the accesses to heavily used sets without dynamically detecting the cache set usage information. We introduce a replacement policy to direct-mapped cache design and increase the access to the underutilized cache sets with the help of programmable decoders. On average, the proposed balanced cache, or BCache, achieves 64.5% and 37.8% miss rate reductions on all 26 SPEC2K benchmarks for the instruction and data caches, respectively. This translates into an average IPC improvement of 5.9%. The B-Cache consumes 10.5% more power per access but exhibits 2% total memory access related energy saving due to the miss rate reductions and hence the reduction to applications' execution time. Compared with previous techniques that aim at reducing the miss rate of direct-mapped caches, our technique requires only one cycle to access all cache hits and has the same access time of a direct-mapped cache.

High-quality ISA synthesis for low-power cache designs in embedded microprocessors

Energy efficiency, performance, area, and cost are critical concerns in designing microprocessors for embedded systems, such as portable handheld computing and personal telecommunication devices. This work introduces framework-based instruction set architecture (ISA) synthesis, which reduces code size and energy consumption by tailoring the instruction set to the requirement of a targeted application. This is achieved by replacing the fixed instruction and register decoding of general-purpose embedded processors with programmable decoders that can achieve application-specific processor performance, low energy consumption, and smaller code size while maintaining the fabrication advantages of a mass-produced single-chip solution. Experimental results show that our synthesized instruction set results in significant power reduction in the L1 instruction cache compared with ARM® instructions.

A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes

A new parameterized-core-based design methodology targeted for programmable decoders for low-density parity-check (LDPC) codes is proposed. The methodology solves the two major drawbacks of excessive memory overhead and complex on-chip interconnects typical of existing decoder implementations and which limit the scalability, degrade the error-correction capability, and restrict the domain of application of LDPC codes. Diverse memory and interconnect optimizations are performed at the code-design, decoding algorithm, decoder architecture, and physical layout levels, with the following features: (1) architecture-aware (AA)-LDPC code design with embedded structural features that significantly reduce interconnect complexity; (2) faster and memory-efficient turbo-decoding algorithm for LDPC codes; (3) programmable architecture having distributed memory, parallel message processing units, and dynamic/scalable transport networks for routing messages; (4) a parameterized macro-cell layout library implementing the main components of the architecture with scaling parameters that enable low-level transistor sizing and power-rail scaling for power-delay-area optimization. A 14 mm/sup 2/ programmable decoder core for a rate- 1/2 , length 2048 AA-LDPC code generated using the proposed methodology is presented; it delivers a throughput of 1.6 Gbps at 125 MHz and consumes 760 mW of power.

An Energy Efficient Instruction Set Synthesis Framework for Low Power Embedded System Designs

Energy efficiency, performance, area, and cost are critical concerns in designing microprocessors for embedded systems such as portable handheld computing and personal telecommunication devices. This work introduces the concept of framework-based instruction set synthesis (FITS), which is a new instruction synthesis paradigm that falls between a general-purpose embedded processor and a synthesized application specific processor (ASP). FITS processors reduce code size and energy consumption by tailoring the instruction set to the requirement of a target application. This is achieved by replacing the fixed instruction and register decoding of a general purpose embedded processor with programmable decoders that can achieve ASP performance, low energy consumption, and smaller code size with the fabrication advantages of a mass produced single chip solution. Experimental results show that our synthesized instruction sets result in significant power reduction in the level one instruction cache compared to ARM instructions. The instruction cache is one of the most predominant sources of power dissipation on the processor. For instance, in Intel's StrongARM processor, 27 percent of total chip power loss goes into the instruction cache. For 21 MiBench benchmarks, our simulation results, indicate, on average, a 49.4 percent saving for switching power, a 43.9 percent saving for internal power, a 14.9 percent saving for leakage power, a 46.6 percent saving for total instruction cache power with up to 60.3 percent saving for peak power.

The implementation and evaluation of dynamic code decompression using DISE

Code compression coupled with dynamic decompression is an important technique for both embedded and general-purpose microprocessors. Postfetch decompression , in which decompression is performed after the compressed instructions have been fetched, allows the instruction cache to store compressed code but requires a highly efficient decompression implementation. We propose implementing postfetch decompression using a new hardware facility called dynamic instruction stream editing (DISE). DISE provides a programmable decoder---similar in structure to those in many IA-32 processors---that is used to add functionality to an application by injecting custom code snippets into its fetched instruction stream. We present a DISE-based implementation of postfetch decompression and show that it naturally supports customized program-specific decompression dictionaries, enables parameterized decompression allowing similar-but-not-identical instruction sequences to share dictionary entries, and uses no decompression-specific hardware. We present extensive experimental results showing the virtue of this approach and evaluating the factors that impact its efficacy. We also present implementation-neutral results that give insight into the characteristics of any postfetch decompression technique. Our experiments not only demonstrate significant reduction in code size (up to 35%) but also significant improvements in performance (up to 20%) and energy (up to 10%).

A DISE implementation of dynamic code decompression

Code compression coupled with dynamic decompression is an important technique for both embedded and general-purpose microprocessors. Post-fetch decompression , in which decompression is performed after the compressed instructions have been fetched, allows the instruction cache to store compressed code but requires a highly efficient decompression implementation. We propose implementing post-fetch decompression using dynamic instruction stream editing (DISE), a programmable decoder---similar in structure to those in many IA32 processors---that is used to add functionality to an application by injecting custom code snippets into its fetched instruction stream. A DISE implementation of post-fetch decompression naturally supports customized program-specific decompression dictionaries, enables parameterized decompression allowing similar instruction sequences to share dictionary entries, and uses no decompression-specific hardware. Cycle-level simulation of DISE decompression shows that it can reduce static program size by 35% and execution time by 20%. Parameterized decompression, a feature unique to DISE, accounts for 20% of the code size reduction by making more effective use of the dictionary and allowing PC-relative branches to be included in compressed sequences. DISE-based compression can reduce total energy consumption by 10% and the energy-delay product by as much as 20%.

Software architecture for flexible and extensible image decoding

Abstract We present a programmable image-decoder architecture for flexible and extensible software implementation. The architecture consists of software modules designed specifically for image-decoding processes, and an interpreter programmable using scripting language. We categorize typical image-decoding processes into bitstream-parsing, image-reconstruction, and data interfacing processes. Since the bitstream-parsing modules and image-reconstruction modules are not coupled in our design, the bitstream syntax can be described solely by bitstream-parsing processes. Moreover, we can modify reconstruction processes without any changes to the bitstream-parsing processes, and vice versa. A script describes an entire sequence of decoding processes, specifying the software modules to be used and their relationships. A set of intermediate codes provides a compact representation of a script. The script interpreter is implemented as a Forth-like stack-based interpreter that selects and executes each module. Adopting the above architecture, we have successfully implemented a programmable software decoder that can perform H.263, MPEG-1 and an original coding scheme that is application-specific.

Analysis of convolutional encoders and synthesis of rate-2/n Viterbi decoders

In this correspondence, the problem of obtaining efficient hardware for Viterbi decoders for high-rate convolutional encoders is addressed. It is first shown that the graphs describing the interconnection of the add-compare-select units required may be classified in terms of structures of which there are only a small number for a given code constraint length. They correspond to the assignment of individual register lengths in the ensemble of shift registers in the feedforward encoder. The structures relate to the partitioning of the states such that common successors are grouped together and successive partitioning leads to a hierarchical, modular VLSI layout method. Example symbolic grid layouts are given for 16- and 64-state codes. It is noted that within a given structure, the parity check matrices map into local wiring patterns implying a method for implementing class-universal programmable or adaptive decoders.

Novel designs of programmable all-optical synchronous code-division multiple-access encoders and decoders

Novel designs of programmable all-optical synchronous code-division multiple-access (CDMA) encoders and decoders are reported. They are based on cascades of optical delay lines and electro-optic switches. The operations of both optical encoders and decoders are illustrated with the well-known prime-sequence codes. Based on the proposed designs, these optical CDMA components can be constructed by integrated optics (i.e., the optical delay lines and switches are all fabricated on the same substrate). With the possibility of mass production and eliminating the fiber-waveguide interface power loss, better cost efficiency and lower power loss would be expected, as compared to the conventional designs.

The iterative collapse algorithm: a novel approach for the design of long constraint length Viterbi decoders. II

For pt.I see ibid., vol.43, no.2/3/4, p.1409-18 (1995). Part I presented the iterative collapse algorithm (ICA) for obtaining a variety of throughput-complexity tradeoffs for the implementation of parallel VDs and demonstrated that better than linear tradeoff can be obtained in this respect for many combinations of the design parameters M and K. Part I also demonstrated that when (MK+1)/spl les//spl nu//spl les/(M+1)K the ACSUs in the design are fully connected. In this case, clustering of the ACSUs makes no sense since it produces a single cluster containing all the ACSUs. The direct implementation of the decoder requires the full interconnection of L/spl les/2/sup K/ ACSUs (i.e., the ACSU topology is that of a fully connected graph on L nodes denoted K/sub L/). For K/spl ges/3 this is a rather challenging task. The present authors provide efficient means of emulating the ACSU interconnections on a linear or a mesh topology array. Such networks are more suitable for implementation in VLSI. The results presented are quite general and may be easily extended to the emulation of other networks with lower degrees of connectivity than that of the complete graph. The technique presented can be used to build programmable decoders for convolutional and trellis codes in addition to making it possible to build multi-chip VDs on a printed circuit board or as a multi chip module. >

A programmable decoder for Reed-Solomon codes

ABSTRACT A programmable decoder for Reed-Solomon codes is described. The decoder is constructed using the Am2900 family of bit-slice elements and it is designed to perform error-correction erasure-filling decoding. The decoding rates obtained, lie in the range of 87 to 22 kilobits per second depending on the code and the error-erasure pattern encountered